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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:34 -0700 Message-Id: <20180915161738.25257-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH 09/13] target/arm: Derive id_pfr1 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0151c278e8..4fb3e0a9ea 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -992,6 +992,31 @@ static uint32_t resolve_id_pfr0(CPUARMState *env) return ret; } +static uint32_t resolve_id_pfr1(CPUARMState *env) +{ + uint32_t ret = 0; + + if (arm_feature(env, ARM_FEATURE_M)) { + ret = deposit32(ret, 8, 4, 2); /* MProgMod */ + } else { + ret = deposit32(ret, 0, 4, 1); /* ProgMod */ + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + ret = deposit32(ret, 4, 4, 1); /* Security */ + } + if (arm_feature(env, ARM_FEATURE_EL2)) { + ret = deposit32(ret, 12, 4, 1); /* Virtualization */ + } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + ret = deposit32(ret, 16, 4, 1); /* GenTimer */ + } + /* Sec_frac -- no partial features implemented without EL3 */ + /* Virt_frac -- no partial features implemented without EL2 */ + /* GIC -- info not available yet; filled in by id_pfr1_read */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1024,6 +1049,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_pfr0; cpu->id_pfr0 = resolve_id_pfr0(env); g_assert_cmphex(cpu->id_pfr0, ==, orig); + + orig = cpu->id_pfr1; + cpu->id_pfr1 = resolve_id_pfr1(env); + g_assert_cmphex(cpu->id_pfr1, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)