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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:37 -0700 Message-Id: <20180915161738.25257-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH 12/13] target/arm: Derive id_aa64pfr0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a9724f3bb1..2ec71104c9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1080,6 +1080,31 @@ static uint64_t resolve_id_aa64isar1(CPUARMState *env) return ret; } +static uint64_t resolve_id_aa64pfr0(CPUARMState *env) +{ + uint64_t ret = 0; + + ret = deposit64(ret, 0, 4, 2); /* EL0 */ + ret = deposit64(ret, 4, 4, 2); /* EL1 */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + ret = deposit64(ret, 8, 4, 2); /* EL2 */ + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + ret = deposit64(ret, 12, 4, 2); /* EL3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_FP16)) { + ret = deposit64(ret, 16, 4, 1); /* FP */ + ret = deposit64(ret, 20, 4, 1); /* AdvSIMD */ + } + /* GIC -- info not available yet; filled in by id_aa64pfr0_read */ + /* RAS -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_SVE)) { + ret = deposit64(ret, 32, 4, 1); /* SVE */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -1122,6 +1147,10 @@ static void resolve_id_regs(ARMCPU *cpu) g_assert_cmphex(cpu->id_aa64isar0, ==, orig); cpu->id_aa64isar1 = resolve_id_aa64isar1(env); + + orig = cpu->id_aa64pfr0; + cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); + g_assert_cmphex(cpu->id_aa64pfr0, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)