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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:38 -0700 Message-Id: <20180915161738.25257-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 13/13] target/arm: Remove assertions from resolve_id_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a prerequisite to removing the now-redundant initializations from within the individual cpus. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 41 +++++++---------------------------------- 1 file changed, 7 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2ec71104c9..79103926a4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1108,49 +1108,22 @@ static uint64_t resolve_id_aa64pfr0(CPUARMState *env) static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; - uint64_t orig; - orig = cpu->id_isar0; - cpu->id_isar0 = resolve_id_isar0(env, orig); - g_assert_cmphex(cpu->id_isar0, ==, orig); - - orig = cpu->id_isar1; + cpu->id_isar0 = resolve_id_isar0(env, cpu->id_isar0); cpu->id_isar1 = resolve_id_isar1(env); - g_assert_cmphex(cpu->id_isar1, ==, orig); - - orig = cpu->id_isar2; - cpu->id_isar2 = resolve_id_isar2(env, orig); - g_assert_cmphex(cpu->id_isar2, ==, orig); - - orig = cpu->id_isar3; + cpu->id_isar2 = resolve_id_isar2(env, cpu->id_isar2); cpu->id_isar3 = resolve_id_isar3(env); - g_assert_cmphex(cpu->id_isar3, ==, orig); - - orig = cpu->id_isar4; cpu->id_isar4 = resolve_id_isar4(env); - /* Willfully ignore the SWP_frac field. */ - g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff); - cpu->id_isar5 = resolve_id_isar5(env); cpu->id_isar6 = resolve_id_isar6(env); - - orig = cpu->id_pfr0; cpu->id_pfr0 = resolve_id_pfr0(env); - g_assert_cmphex(cpu->id_pfr0, ==, orig); - - orig = cpu->id_pfr1; cpu->id_pfr1 = resolve_id_pfr1(env); - g_assert_cmphex(cpu->id_pfr1, ==, orig); - orig = cpu->id_aa64isar0; - cpu->id_aa64isar0 = resolve_id_aa64isar0(env); - g_assert_cmphex(cpu->id_aa64isar0, ==, orig); - - cpu->id_aa64isar1 = resolve_id_aa64isar1(env); - - orig = cpu->id_aa64pfr0; - cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); - g_assert_cmphex(cpu->id_aa64pfr0, ==, orig); + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + cpu->id_aa64isar0 = resolve_id_aa64isar0(env); + cpu->id_aa64isar1 = resolve_id_aa64isar1(env); + cpu->id_aa64pfr0 = resolve_id_aa64pfr0(env); + } } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)