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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:32 -0700 Message-Id: <20180915161738.25257-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike the other id_sar registers, these contain post-v8.0 features that are not included with any existing cpu models. They would be enabled by -cpu max when we enable them for system mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3c6ddd6532..c227044946 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -926,6 +926,49 @@ static uint32_t resolve_id_isar4(CPUARMState *env) return ret; } +static uint32_t resolve_id_isar5(CPUARMState *env) +{ + uint32_t ret = 0; + + /* SEVL -- we always implement as NOP. */ + /* AES */ + if (arm_feature(env, ARM_FEATURE_V8_PMULL)) { + ret = deposit32(ret, 4, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_AES)) { + ret = deposit32(ret, 4, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_V8_SHA1)) { + ret = deposit32(ret, 8, 4, 1); /* SHA1 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SHA256)) { + ret = deposit32(ret, 12, 4, 1); /* SHA2 */ + } + if (arm_feature(env, ARM_FEATURE_CRC)) { + ret = deposit32(ret, 16, 4, 1); /* CRC32 */ + } + if (arm_feature(env, ARM_FEATURE_V8_RDM)) { + ret = deposit32(ret, 24, 4, 1); /* RDM */ + } + if (arm_feature(env, ARM_FEATURE_V8_FCMA)) { + ret = deposit32(ret, 28, 4, 1); /* VCMA */ + } + + return ret; +} + +static uint32_t resolve_id_isar6(CPUARMState *env) +{ + uint32_t ret = 0; + + /* JSCVT -- not implemented yet */ + /* FHM -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) { + ret = deposit32(ret, 4, 4, 1); /* DP */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -951,6 +994,9 @@ static void resolve_id_regs(ARMCPU *cpu) cpu->id_isar4 = resolve_id_isar4(env); /* Willfully ignore the SWP_frac field. */ g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, ==, orig & 0x0fffffff); + + cpu->id_isar5 = resolve_id_isar5(env); + cpu->id_isar6 = resolve_id_isar6(env); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)