From patchwork Mon Oct 8 21:22:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148452 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4136871lji; Mon, 8 Oct 2018 14:31:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV60bZpcqfnMFkXls7HfgpwwesF/sM4edSSnjx2pXitPa0IGIrbmEUIZmkHApJhOebQ0WLiRf X-Received: by 2002:a0c:b899:: with SMTP id y25-v6mr20263714qvf.230.1539034311791; Mon, 08 Oct 2018 14:31:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539034311; cv=none; d=google.com; s=arc-20160816; b=a+M880L1NQbZKML64h6V+9A9bJUx32l+rvD22F8F8c4BICNcDqdJrtrZSp9dAfQ/mG Rmu5VJlSqCNqAbck9MA3yoWvegUrsAmFxQUc9+R42+1Y+ZQ1mfy5Gg217nQnOWqcgEGK umNoWonQirZstkGUoTaE9gJNo98ac0N6S8dz7kruBEjIAqyJxratEdTP1SzE7tQV2CyV c4ag+0KyIeb+e14fYwMbdB/p0l5Wl3mMfPN/Qw0LEsLkdLoIyT2v+4BFp6SZnqhEYwn4 hJvDJR2OQbdX27ISimfZRjdOvp619nr3/bACBau5ic6lE3gkdWpFs0fT9VaAWRuYUoqE OxOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=roUyvyUvAC73WofL39mfPtaFRJ3F01ciD4oZ0U4D0KQ=; b=zjFQ7MW/vqFhj6qvZMCVqdBtRDCAnwCgYJ/dGp0msKtOkjmsH/oM8S6mSLnjPRGcJd RjFfzyKCVuyK2FbyFBC9CEPTUuo9vkM56R05jx7K6AAtJKme/UKtw+ZDDX9j6j0+wxSN aGBEt0sH3V48MKzEFK+yB1wYw1K3Y0WazxNFY6VJ6waRpBRd7S2Q2QOmlFnWOR9peFQp UquzZsD1tiVBIxpNZFSZcQCv1aUFMmBRRAl/0QwZP0vP8OiGTkBh6s9rrxAtFY7LTJ9b zm/ldsUQBuVUmVcCohlegxyaW6XC97XlIhnUAiLIkrGSSRrZXJzeqgnDp8hperqAw8Al 4/+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZDC1XNgF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id z1-v6si2872154qtd.127.2018.10.08.14.31.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 08 Oct 2018 14:31:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZDC1XNgF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48393 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9d83-0007lV-5x for patch@linaro.org; Mon, 08 Oct 2018 17:31:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9d4S-000559-Ht for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:28:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9cyr-0008AQ-1j for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:22:24 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:42529) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g9cyq-00089L-Pd for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:22:20 -0400 Received: by mail-pf1-x434.google.com with SMTP id f26-v6so8787748pfn.9 for ; Mon, 08 Oct 2018 14:22:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=roUyvyUvAC73WofL39mfPtaFRJ3F01ciD4oZ0U4D0KQ=; b=ZDC1XNgFfGBkjry8qtisMuI2gHMe/A5mMwsD3JaCMZIC/1S2DIBCE8nW0sPJOGP54w RPUjAXTtweAZZlwem/mOLzCTWXmZQqKzQJODftdPobNHGCqOF4XyU6t4JleiB7sxS9Cw bb947ZJrHm6ULSxVXNYiPwfdT0wmNP1rHrEjM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=roUyvyUvAC73WofL39mfPtaFRJ3F01ciD4oZ0U4D0KQ=; b=BfpBuKEFcOFF7r9U55SOHuLNb+I7FBdpDHCAG1sOvXiwsT9/I+tbyr9kBGwiyFcoE9 PEY+L4DDnsJ617JNWZdoRcW/PtBA8FbJxqRxl44g4MqyYpWrgExNPnGwQaMqn63pBSkd j90RYtCflcgzEbal8Aeuq8wl5LbZnTOpVQWZkzSIBzIIvgUjzK9quMBNPT5CaBZ/AXVI cVStwlb44A7/6DMJ8ehMpdbDPtFQbYHe6its3clyczo/RiUuKWSnuCcyKzJ/N0BfGjMm W8nL+59rMGiggGtz18zm4b5KDML6AXLqpXhm0wQCFZUJtMzADoAgEm/HK9wx3eOtKdp9 21jQ== X-Gm-Message-State: ABuFfogLTVtLet2aF3IqAsColcxAjSBG/WYBmFcjDcfieuY7crfpN71i IEYHT1lFSPQ3pfZwn83ZFNKlzTBHgtI= X-Received: by 2002:a62:9ec7:: with SMTP id f68-v6mr27323545pfk.206.1539033738486; Mon, 08 Oct 2018 14:22:18 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id r25-v6sm20392913pgm.59.2018.10.08.14.22.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 14:22:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 14:22:02 -0700 Message-Id: <20181008212205.17752-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008212205.17752-1-richard.henderson@linaro.org> References: <20181008212205.17752-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH v3 07/10] target/arm: Convert jazelle from feature bit to isar1 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. This was harmless, because the only place we tested ARM_FEATURE_JAZELLE was for 'bxj' in disas_arm(), which is unreachable for M-profile cores. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- target/arm/translate.h | 1 + target/arm/cpu.c | 17 ++++++++++++++--- target/arm/translate.c | 2 +- 4 files changed, 21 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2af971e823..557ef8daf9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1580,7 +1580,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ @@ -3147,6 +3146,11 @@ static inline bool aa32_feature_arm_div(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) > 1; } +static inline bool aa32_feature_jazelle(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) != 0; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) != 0; diff --git a/target/arm/translate.h b/target/arm/translate.h index 8279465d1d..bd394bdf69 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -197,6 +197,7 @@ static inline TCGv_i32 get_ahp_flag(void) FORWARD_FEATURE(thumb_div) FORWARD_FEATURE(arm_div) +FORWARD_FEATURE(jazelle) FORWARD_FEATURE(aes) FORWARD_FEATURE(pmull) FORWARD_FEATURE(sha1) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f068b4c476..4e2609aa7e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -850,8 +850,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_JAZELLE); if (!arm_feature(env, ARM_FEATURE_M)) { + assert(aa32_feature_jazelle(cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } @@ -1078,11 +1078,16 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x41069265; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->id_isar1 = FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); } static void arm946_initfn(Object *obj) @@ -1108,12 +1113,18 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x4106a262; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; cpu->reset_auxcr = 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->id_isar1 = FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); + { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ ARMCPRegInfo ifar = { diff --git a/target/arm/translate.c b/target/arm/translate.c index b1ee6533cc..54ecf369cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) +#define ENABLE_ARCH_5J aa32_dc_feature_jazelle(s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)