From patchwork Fri Oct 12 14:42:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148779 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819443lji; Fri, 12 Oct 2018 07:42:50 -0700 (PDT) X-Google-Smtp-Source: ACcGV63zTAnhDJJolkM9aJdI2LKowEJ/qxuYc/Js/uQvfstp3IMC0qy36SLFgtvHJ1S/G0CVjxn7 X-Received: by 2002:adf:8103:: with SMTP id 3-v6mr5424165wrm.106.1539355370804; Fri, 12 Oct 2018 07:42:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355370; cv=none; d=google.com; s=arc-20160816; b=abYphch3ASyxfPFpzu+0PF58kSTKx+mjRhQ2gDXLKTWrqQ+icc9OaLnRCrwb4tUx1T ZFIrIHDVuZM2rGJjuTDJ6ctk7LHgEN+H8yqc6iCU9eNdL4GGqMJpvU4NlKW/JTwISN5b WPpY6P1wl/pbcFKsbCUi8wEIwMWs84lvtR7JqGoYH6RCBDszuolVPEomWB7GjEluezHD N2zaYJdT6caUYf0zPILNapJynnFFxCB33nIWNxuKF/oH9UYyUBZIlnwV3fIR0PjnT0hU 2TrwCdYb1fuv0EJVpTwLgE9h/jvR+/WUoIbLLsHvvnNWyDzVtkpqlcaxGs+exAE6ephR +Hqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=iou+UBXP+eQFdyool2gb/5TStsa+qgoBYA3ItGGn5wY=; b=Qu27+JXJMGqEM8HKYGsLwc104m1zQ2ymaWow+7L2cbg9w9BCw21PKd8CJ5//pxmEwG nEqjRfOMzj90JvwgBxAEmC41ASb9lEMmISZZCjjz871P3ytbpmZDeQwPjSBCZ/pZl7Mn pxg9VNxP3UhlZFPRfh/ajr5jWbqfVo2yvrWz8FKJb+nLWmrHBfxV6tBwnSAcQgH5Rq0J FrRhKVi/kgjIplqpOscAB6TUroMLMW88lozSVzjY9UxV03FzL6+zBVgKHM6lotu8ktWI Y32oFMDFK26AHEJ3Ox5aKvyJWXE5ECnIwqq1ZPc4H9zBnG/2UIsvNafuuppDwm+jETM+ O3Rw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d17-v6si1225769wrs.188.2018.10.12.07.42.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeQ-0000QD-BJ; Fri, 12 Oct 2018 15:42:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode Date: Fri, 12 Oct 2018 15:42:35 +0100 Message-Id: <20181012144235.19646-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome provided in HSR has more information than is reported to AArch64. Specifically, there are extra fields TA and coproc which indicate whether the trapped instruction was FP or SIMD. Add this extra information to the syndromes we construct, and mask it out when taking the exception to AArch64. Signed-off-by: Peter Maydell --- target/arm/internals.h | 14 +++++++++++++- target/arm/helper.c | 9 +++++++++ target/arm/translate.c | 8 ++++---- 3 files changed, 26 insertions(+), 5 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index cd8bc1ec3d4..960dfb3c06a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -288,6 +288,9 @@ static inline uint32_t syn_get_ec(uint32_t syn) * few cases the value in HSR for exceptions taken to AArch32 Hyp * mode differs slightly, and we fix this up when populating HSR in * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra coproc + * and TA fields, and mask them out when taking the exception to AArch64. */ static inline uint32_t syn_uncategorized(void) { @@ -387,9 +390,18 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) { + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20); + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 SIMD trap: TA == 1 coproc == 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); } static inline uint32_t syn_sve_access_trap(void) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b659171b07..43afdd082e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8540,6 +8540,15 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) case EXCP_HVC: case EXCP_HYP_TRAP: case EXCP_SMC: + if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); + } env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c7d920e331..d71597796f5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4948,7 +4948,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -5727,7 +5727,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -7840,7 +7840,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } if (!s->vfp_enabled) { @@ -7926,7 +7926,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } if (!s->vfp_enabled) {