From patchwork Fri Oct 12 14:42:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148771 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819276lji; Fri, 12 Oct 2018 07:42:41 -0700 (PDT) X-Google-Smtp-Source: ACcGV632LSH3IXTGnMPw6P2ujgaKMA7LVqMFC/CQ0cB1DspDoRvHOx1O/cVdIZjekkM+6kZfrpxC X-Received: by 2002:adf:e70f:: with SMTP id c15-v6mr5945299wrm.165.1539355361046; Fri, 12 Oct 2018 07:42:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355361; cv=none; d=google.com; s=arc-20160816; b=Xcb7W214mVjFz3eMNvoLBSEDv/oROjt9yawppUEBFHukNTAAOGiass+vGWhT3jcGj3 5sNVXcYbyQsx0wW2dIKXu2EZ8fQR/qcTQf+azDIDx8k1FbbOtUTVHm3JfdRC9qM4MkoZ oc+0N3/hr3+60ep/sM9yjifl/nqX00qxkPQ6yKvwn6x/Zgz4t+G/FUE5jHKZlFeZk5Or 4HnsQqKjLnbGXFKODEOVZnrki7lprPS7AUfVqYCOvUrM5eurK+cIr9ODTR8bKOAi+Buq uNIxSL4ymE70TXxCCwp0gQKWA61Y8ThTjClBP3cn7FZ8RFUCSgs5XCuaiEAhBYsWhcbG MQXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=5NELGqkVegsuFLiL+w9oa4KbdKG/pxd6jjvzB2xcjf8=; b=urCTW7OnA0cxK8FL3n5oDyXaJ+3a7PHrR2oE6zDNuwibUaaIKj8KiQtcCfiSq4DTmn SutLIZpTXRNic+k/0KBt/SzWGnrbUBqC8zQcJZrjJT9fZlW3Lo8/i/Hjn1eO7kLLs6aC MjpOGFT7A/JaXAhJekl3Kcz0gZAJ/nzPNOAPE2gvrGaIcgACMbTMDPzfYAPmdNc/QhuD WRqbF35oiXJEECcqbCL+bVxe+o2IQJLd/shwT0dzKzYeBwxSgzskkrW4TwUcBcq2Zfwh ABqw243q8iv/Rdk+25qTYs6xzUA0f02YU7/QN0XaP/gs3+ALpQqm/DChpS91mzGvMCrR i02w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j13-v6si1157947wmh.61.2018.10.12.07.42.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeG-0000O3-FA; Fri, 12 Oct 2018 15:42:40 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 02/10] target/arm: Make switch_mode() file-local Date: Fri, 12 Oct 2018 15:42:27 +0100 Message-Id: <20181012144235.19646-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The switch_mode() function is defined in target/arm/helper.c and used only in that file and nowhere else, so we can make it file-local rather than global. Signed-off-by: Peter Maydell --- target/arm/internals.h | 1 - target/arm/helper.c | 6 ++++-- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index abe4d73b59c..d4b1973efa1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -145,7 +145,6 @@ static inline int bank_number(int mode) g_assert_not_reached(); } -void switch_mode(CPUARMState *, int); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fa5ac0450f..0253a971099 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -56,6 +56,8 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, V8M_SAttributes *sattrs); #endif +static void switch_mode(CPUARMState *env, int mode); + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -6313,7 +6315,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return 0; } -void switch_mode(CPUARMState *env, int mode) +static void switch_mode(CPUARMState *env, int mode) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -6335,7 +6337,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) #else -void switch_mode(CPUARMState *env, int mode) +static void switch_mode(CPUARMState *env, int mode) { int old_mode; int i;