From patchwork Fri Oct 12 14:42:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148774 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819374lji; Fri, 12 Oct 2018 07:42:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV61TMXKyPf0X07y3W/3oMIejal4tn/ybL06myLbG6qVP3IWTSXy5x7twOsJbtn2NkOtCsYYd X-Received: by 2002:adf:9206:: with SMTP id 6-v6mr5693866wrj.275.1539355366003; Fri, 12 Oct 2018 07:42:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355365; cv=none; d=google.com; s=arc-20160816; b=Hh2clG8DdmXJ7xvCRUSMfzlgnyMkR0Wbsky7K+Y+y/+iZ4PJzyhwhULsy7aCHVzQfL uH+PR9O5oxL2DCD+9a+hhLTc1C15HZwBn3hfV9/aaTI9EeDkYY4QNuLwLxrCoY9Nh078 Lb7PiwmKeOxKnr7D3j/ZGoqlYvNS1ref6Ud5Or20MNsioLrNEyShzt83p6cKbI6KAVBz /xjQgAQuWzxy5yFQZGJA40VMtwaH+HxkQJefjHPT8ALg3ukhqAzUfvz01H+S8WK9tdUd OMX1XILuiMTST7w/IGlK/W2LTr8AbOhF3Nw7pKPyikuLMHoEKdxsguv5i16CkoLvLJz+ XawA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=JZH/Kjnru7jKz33s+DuzqVq7dopxuu2ZiwaPLzptua8=; b=PKgdT8NffeyW8NzGsq7LWELse76+1lngv1ORcPIwrGC3UqujvjyI3QX1NYoELdtbBJ B6fIas0GTiuT6YF/C3tl3JjBLwmLWoK5dV94xuVByw2+5Et+r4fzk1dW+blTzILjZD1S G5PK1MsdLi6WTpMPdtMceysbww67lNZLGqoSFCdyPZAQSdBmYlJH7w8bqv18F7Vn+dQ9 ceFwpiNXDcGjZZIM4sTS95cgSNSzOPwDx6VEvDIqdBZner8s2CuoJsjIDxCZNqsBBEJp azoaaarLAZG0LQnKuHyRUqiYtvjnPzG5RABH70i+xLejm2FrwmhWchR+T9tSKHHpS43u J3gw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id i2-v6si1290938wrb.392.2018.10.12.07.42.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeL-0000Ow-II; Fri, 12 Oct 2018 15:42:45 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 05/10] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set Date: Fri, 12 Oct 2018 15:42:30 +0100 Message-Id: <20181012144235.19646-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The A/I/F bits in ISR_EL1 should track the virtual interrupt status, not the physical interrupt status, if the associated HCR_EL2.AMO/IMO/FMO bit is set. Implement this, rather than always showing the physical interrupt status. We don't currently implement anything to do with external aborts, so this applies only to the I and F bits (though it ought to be possible for the outer guest to present a virtual external abort to the inner guest, even if QEMU doesn't emulate physical external aborts, so there is missing functionality in this area). Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 84b40031b6f..65e431e03b3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1328,12 +1328,26 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) CPUState *cs = ENV_GET_CPU(env); uint64_t ret = 0; - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - ret |= CPSR_I; + if (arm_hcr_el2_imo(env)) { + if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + ret |= CPSR_I; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + ret |= CPSR_I; + } } - if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { - ret |= CPSR_F; + + if (arm_hcr_el2_fmo(env)) { + if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + ret |= CPSR_F; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { + ret |= CPSR_F; + } } + /* External aborts are not possible in QEMU so A bit is always clear */ return ret; }