From patchwork Fri Oct 12 14:42:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148777 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819415lji; Fri, 12 Oct 2018 07:42:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV600AA1VuKWBIh5L8BavcIqLIcuSiSDcQpOr69YMCa4J5CAqW7XvRBVBRnAcZGiDMcvC5BWw X-Received: by 2002:adf:f14a:: with SMTP id y10-v6mr5430935wro.29.1539355368925; Fri, 12 Oct 2018 07:42:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355368; cv=none; d=google.com; s=arc-20160816; b=vYDIUdIZSRMtRLldGTYB5a1LFtTRU5jsh1SO84v1stxF+zoUw3N4gX+eO1zTa4xCbj cqPG2xWJLZD6NFjHp2fnSwOJiuloTLDi0TUJNst8jDAvwjw6Ip9r8heMM+uMTb9O+mwe v3Iwu61pVrKavlDg8LM4yl9iH6+p8tkv5XpPG1QD6Tma60+ZnW5FHGY/YVydVAqLFlGW xewuRhyD8K6ZRqTsbWftq/DPvVKquCB6SoeARk/oAzbC2LfLJqsL6O+whwj+DXjaBZXy 5g3ppPKaoRnkvMturnOTLVZa5GA1YnM3J6ksTr90FOKQyc0XBjxHAMsBAnZx7SIgeTsh KdbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=H+vkl/qzeenehwtysQ8Hz+5KAKjqPVse5tygDQbTdDI=; b=Uj5LeacqokIFavcpx0VSVEzfpLaCkVZAKu0vdSSoy9ShuLegarFAkxeBS76/rbXq2G BGo71dgSWBruWr5xXrVBilwjL0l4rhlBjOtowr0GRz5lZY+T8jaOtd1w9FtPc3jc7c+o WFw/ki2AZ+TMio5BeRGnrt8IxoOBf0yLgPxEGdHuVIyuBnTY3vZlE59mjwuzlnYd+oeA YYQ4kqY8U+KLRkJDr1UTBLPlr3NcopcTs54fnegVc0c50pU2c6hmdPorFDEve6j3ddg7 GquvDXQSPkfthP5mzfXptIC8OFD36elwx+C5Y2sGOVNgwS2OxGUl23ALbc48hafv0qr1 aL/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j1-v6si1276559wrg.455.2018.10.12.07.42.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeO-0000Pg-EI; Fri, 12 Oct 2018 15:42:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 08/10] target/arm: New utility function to extract EC from syndrome Date: Fri, 12 Oct 2018 15:42:33 +0100 Message-Id: <20181012144235.19646-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 Create and use a utility function to extract the EC field from a syndrome, rather than open-coding the shift. Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 +- target/arm/op_helper.c | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index d4b1973efa1..516f9454e9b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -278,6 +278,11 @@ enum arm_exception_class { #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + /* Utility functions for constructing various kinds of syndrome value. * Note that in general we follow the AArch64 syndrome values; in a * few cases the value in HSR for exceptions taken to AArch32 Hyp diff --git a/target/arm/helper.c b/target/arm/helper.c index b5752d52dd1..0b89804961b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8333,7 +8333,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) uint32_t moe; /* If this is a debug exception we must update the DBGDSCR.MOE bits */ - switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { + switch (syn_get_ec(env->exception.syndrome)) { case EC_BREAKPOINT: case EC_BREAKPOINT_SAME_EL: moe = 1; @@ -8669,7 +8669,7 @@ void arm_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", - env->exception.syndrome >> ARM_EL_EC_SHIFT, + syn_get_ec(env->exception.syndrome), env->exception.syndrome); } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e0b82462838..ce33cbc65a6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -920,7 +920,7 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) { - int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT; + int hsr_ec = syn_get_ec(debug_exit->hsr); ARMCPU *cpu = ARM_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index fb15a13e6c9..b1e65f43d38 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -42,7 +42,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, * (see DDI0478C.a D1.10.4) */ target_el = 2; - if (syndrome >> ARM_EL_EC_SHIFT == EC_ADVSIMDFPACCESSTRAP) { + if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { syndrome = syn_uncategorized(); } }