From patchwork Wed Oct 24 11:37:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149493 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp475431ljp; Wed, 24 Oct 2018 04:43:54 -0700 (PDT) X-Google-Smtp-Source: AJdET5dG6PG+APjwnXERdU/hp3vgSzFi6H/jHcvjho06SWfDutJD7HJfqlCMqhnWtAtwVl0ZpAK/ X-Received: by 2002:a0c:cdc2:: with SMTP id a2mr2032606qvn.74.1540381434316; Wed, 24 Oct 2018 04:43:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540381434; cv=none; d=google.com; s=arc-20160816; b=R10B+FnvNuShPqZ6WPiWomk+cnahhRES1NSnU++72f7fTRdhE7biezj1j4TPeDbAZ4 1kG2DWaI1gtCsgXQvMuLIYr+o9jY7B+OXQ9ZV6HPEEEkswaaU95nGoXeSyy7xyhhMhyG tbSdLvyIMxxXDoAuS+XmfkagfHmFQheuo+CTVAJVF3xIYw92xPQqZNwMDSnSA3eRCIYL Ji6ZS6iA9yeuAEOOcGzJTa/WzKwjI0K5FKwdXpkC3s2RaxSxXEIJb3zzc1TIoD3TkVHO rfbXyV701lex7Ijul6vCNgxrjQQi3QiZ5fU939T2OSJmzJLpuVKOzO2aG/W4xNHryR5w FsOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=alNykdPhAmQGBw8DApolghGIOI94fJkHQN66o4S0f1E=; b=LAg6ACjubKWabDEEDyBmwHLX8n4CaOyM9LKLteJGwJ8x1DN/7O9WquzOvPZy7kWujV hg/kXFebKeisF+/beWyRAS96FYlf9ug/RUTRpKVZeBQOn52vDu9ROBNlNLFF8VwcpNLw xUEWTjEDZShXF2YvR5u0d1cZW7VyUFv0Ao8CTV0tJ5Z4Jvx1HK7+ZgMzfZSA1NKZZO2n VRFk2+nhxwHIsCC7/jqIzQgD5GzXj7Q65R+ix3Y7glvGvEfjLu9U/gZZNSrBWNbgXmYi kTrdDQfGF1zijivvcXni4yQq+Rnem4suYrhnhmH/IC6UaKJUjV2/WwqSvDCxz7k4wUz/ YCzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JXtHu2mE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s3-v6si219366qvb.138.2018.10.24.04.43.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 24 Oct 2018 04:43:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JXtHu2mE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47695 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHZp-0001K5-NE for patch@linaro.org; Wed, 24 Oct 2018 07:43:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHTm-0003HY-F2 for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFHTk-0005HU-TV for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:38 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39136) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gFHTk-0005DS-KO for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:36 -0400 Received: by mail-wm1-x343.google.com with SMTP id y144-v6so5013872wmd.4 for ; Wed, 24 Oct 2018 04:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=alNykdPhAmQGBw8DApolghGIOI94fJkHQN66o4S0f1E=; b=JXtHu2mE7SIdRa0mllo2Ki17wkqv9qiSMcoB4MFG95VT454G/fzumNYF4Np8+rXDjV APz108S5aDKej7KLl3Zu4BHrEUUcj4I5Sx7VK5lvoYYTKH3yse9qBxazDqt6PgiaKBo+ vRWZH5z5lDOZ7FfRFj2sy+bOpi5bqTZOsdlm4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=alNykdPhAmQGBw8DApolghGIOI94fJkHQN66o4S0f1E=; b=oh+nCaToSNjilyD0s2qMXmgNJMNMbiqsGFGvphm3IvQzA2OFC3zb9H7CIFlaoRer0O gJx1SvlvuaRlWmsIaFdl6wMMGBmDVMp0epwWPLOemOh1ag0xKLBsD+ZAPQIMTK3m2ilj 7tz75IajqP/8X6ecaSnC2Lvw7StX5S2M4qvjH1y56+tzA+AGOcpjoMiopR5se9TXsA5E RLCggGctFzkbQT248ZaHtXDHh/CMKInwGvuVK6nHYL6XPPNA0ambrdH9bt3MnGjzEnOp rFr0CEZz1/iBL8pZziGUyyrumB48V2lLlVBNltraA6xuRAQaVjrIZWrcq3/ceY9nNqmM H7Og== X-Gm-Message-State: AGRZ1gKzRwIk14IO/gN+/i9Y8k7RQInhvpdgpYOMxls72yM+ASiq+4P9 TZhEv7AlrGCbVKD4afheEgA6fewMi7w= X-Received: by 2002:a1c:3403:: with SMTP id b3-v6mr2296125wma.108.1540381045315; Wed, 24 Oct 2018 04:37:25 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([185.7.230.213]) by smtp.gmail.com with ESMTPSA id c8-v6sm6769172wrb.6.2018.10.24.04.37.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Oct 2018 04:37:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:09 +0100 Message-Id: <20181024113709.16599-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 5/5] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/kvm32.c | 3 --- target/arm/machine.c | 3 +-- 6 files changed, 8 insertions(+), 12 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..895f9909d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1575,7 +1575,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3172,6 +3171,11 @@ static inline bool isar_feature_jazelle(const ARMISARegisters *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; } +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) != 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 055f6a95ab..45d6836bb9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..e08a2d2d79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1440,7 +1440,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; @@ -1509,7 +1508,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1572,7 +1570,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1618,7 +1615,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..bea4d5350d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5455,7 +5455,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f23cc77d9e..bf39937a08 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -115,9 +115,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); - if (extract32(id_pfr0, 12, 4) == 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); - } if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..07f904709a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -321,9 +321,8 @@ static const VMStateDescription vmstate_m = { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu = opaque; - CPUARMState *env = &cpu->env; - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } static const VMStateDescription vmstate_thumb2ee = {