diff mbox series

[v2,1/6] target/arm64: properly handle DBGVR RESS bits

Message ID 20181108163329.19940-2-alex.bennee@linaro.org
State Superseded
Headers show
Series KVM Guest Debug fixes (plus TCG EL2 debug tweaks) | expand

Commit Message

Alex Bennée Nov. 8, 2018, 4:33 p.m. UTC 
This only fails with some (broken) versions of gdb but we should
treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's
reference copy of dbgbvr and also update the register descriptions in
the comment.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>


---
v2
  - sanitise register on insertion
  - update reference description
---
 target/arm/kvm64.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

-- 
2.17.1

Comments

Richard Henderson Nov. 8, 2018, 5:09 p.m. UTC | #1 
On 11/8/18 5:33 PM, Alex Bennée wrote:
> -        .bvr = addr

> +        .bvr = sextract64(addr, 52, 53)


I think you meant sextract64(addr, 0, 53).
What you wrote *should* have asserted, since 52+53 > 64.


r~
Alex Bennée Nov. 8, 2018, 5:30 p.m. UTC | #2 
Richard Henderson <richard.henderson@linaro.org> writes:

> On 11/8/18 5:33 PM, Alex Bennée wrote:

>> -        .bvr = addr

>> +        .bvr = sextract64(addr, 52, 53)

>

> I think you meant sextract64(addr, 0, 53).

> What you wrote *should* have asserted, since 52+53 > 64.


Dam, I did fix that. I must have failed to propagate the fix from where
I was hacking :-/

>

>

> r~



--
Alex Bennée
diff mbox series

Patch

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 5de8ff0ac5..b92ce3437f 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -103,7 +103,7 @@  static void kvm_arm_init_debug(CPUState *cs)
  * capable of fancier matching but that will require exposing that
  * fanciness to GDB's interface
  *
- * D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
+ * DBGBCR<n>_EL1, Debug Breakpoint Control Registers
  *
  *  31  24 23  20 19   16 15 14  13  12   9 8   5 4    3 2   1  0
  * +------+------+-------+-----+----+------+-----+------+-----+---+
@@ -115,12 +115,25 @@  static void kvm_arm_init_debug(CPUState *cs)
  * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
  * BAS: Byte Address Select (RES1 for AArch64)
  * E: Enable bit
+ *
+ * DBGBVR<n>_EL1, Debug Breakpoint Value Registers
+ *
+ *  63  53 52       49 48       2  1 0
+ * +------+-----------+----------+-----+
+ * | RESS | VA[52:49] | VA[48:2] | 0 0 |
+ * +------+-----------+----------+-----+
+ *
+ * Depending on the addressing mode bits the top bits of the register
+ * are a sign extension of the highest applicable VA bit. Some
+ * versions of GDB don't do it correctly so we ensure they are correct
+ * here so future PC comparisons will work properly.
  */
+
 static int insert_hw_breakpoint(target_ulong addr)
 {
     HWBreakpoint brk = {
         .bcr = 0x1,                             /* BCR E=1, enable */
-        .bvr = addr
+        .bvr = sextract64(addr, 52, 53)
     };
 
     if (cur_hw_bps >= max_hw_bps) {