From patchwork Fri Nov 9 13:47:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150643 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp189433ljp; Fri, 9 Nov 2018 05:47:40 -0800 (PST) X-Google-Smtp-Source: AJdET5eApoyj1Bbhb4gwTQkTY2CK4xkaymUD3saUe/3dJJCZp6TzgG+Un7ne4s0rMP9KqO10cHpS X-Received: by 2002:a17:902:4643:: with SMTP id o61-v6mr8784730pld.43.1541771260601; Fri, 09 Nov 2018 05:47:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541771260; cv=none; d=google.com; s=arc-20160816; b=jlmMcljAItvhOdeMIQ/c+tkWwAnDKQBI+UCNhWtiapnY0bVLJi/PCUTCRKIkaB1odW LnF/oueYL2S3BOS5dsCLzyOUBaXmrdbw620NKjxluIkjk4MHTLZQPdkeCGm8lGKECf3y eomabQ7gVU+I688kbRiSn5Mto8N2Rmp0xYzBmmvhHx3e1yRVVKkGFDcXr+hsJhHpJQZL wtjVyoHOh3ZsED0+AVYo5OMgQioVg6EUoDu/NjcPMa6Loqv+tYYRPgNSMUUDWmEu4L7l CxXtnaU8bgFj3By2vxzVx8IKXn93iSjum26kfO31uYiwQmsHeGuxSBYC+yiq6TPxWTtU z+Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=f0k6Vy4SZenDQYnqHnq78LUZZiLS1wcpJQ6I2rWlfz0=; b=qS+buFFeGh/CYxp9ZfejiMhdiL0oVgeovQG4GdfRVb5LlPCpxdY42dkARmYQVXm7kJ t6J3L9zTP/sA9RxyIiY/GZvIAIaBcjZQ8r29Fz/0/1ppvJ/z2YelsnCrrdNzx6nWypQ7 VqU8uqiB+wu52Y/255mdWKa11jzpeCWxzIOkDv7Gx2YvEbaVzVPOVKc92pUtESCJSdCe DhiNJb461rsMuOmrHp09CYx+6WP5RwODU8JBuWs7ljbYi8rqGYW6tE4fAsLCAEDMHPqi fQ2Xq7UePAx0eSk5wfKq6bbtM4VRNAgeXmzhj0haT0nCnUlkawskiAy/ANgxkSh2/4Zm 1egw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id ba2-v6si7667437plb.88.2018.11.09.05.47.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Nov 2018 05:47:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gL78J-0002kN-ML; Fri, 09 Nov 2018 13:47:35 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Adam Lackorzynski Subject: [PATCH for-v3.1 1/3] Revert "target/arm: Implement HCR.VI and VF" Date: Fri, 9 Nov 2018 13:47:29 +0000 Message-Id: <20181109134731.11605-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109134731.11605-1-peter.maydell@linaro.org> References: <20181109134731.11605-1-peter.maydell@linaro.org> MIME-Version: 1.0 This reverts commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29fc231 would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. As a preliminary to implementing the HCR.VI/VF feature properly, revert the broken one entirely. Signed-off-by: Peter Maydell --- target/arm/helper.c | 47 ++++----------------------------------------- 1 file changed, 4 insertions(+), 43 deletions(-) -- 2.19.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 851ea9aa977..f3878f505b7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3931,7 +3931,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = ENV_GET_CPU(env); uint64_t valid_mask = HCR_MASK; if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -3950,28 +3949,6 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &= valid_mask; - /* - * VI and VF are kept in cs->interrupt_request. Modifying that - * requires that we have the iothread lock, which is done by - * marking the reginfo structs as ARM_CP_IO. - * Note that if a write to HCR pends a VIRQ or VFIQ it is never - * possible for it to be taken immediately, because VIRQ and - * VFIQ are masked unless running at EL0 or EL1, and HCR - * can only be written at EL2. - */ - g_assert(qemu_mutex_iothread_locked()); - if (value & HCR_VI) { - cs->interrupt_request |= CPU_INTERRUPT_VIRQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - } - if (value & HCR_VF) { - cs->interrupt_request |= CPU_INTERRUPT_VFIQ; - } else { - cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ; - } - value &= ~(HCR_VI | HCR_VF); - /* These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups @@ -3999,32 +3976,16 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } -static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* The VI and VF bits live in cs->interrupt_request */ - uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF); - CPUState *cs = ENV_GET_CPU(env); - - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { - ret |= HCR_VI; - } - if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { - ret |= HCR_VF; - } - return ret; -} - static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, - .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write, .readfn = hcr_read }, + .writefn = hcr_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_writelow, .readfn = hcr_read }, + .writefn = hcr_writelow }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, @@ -4261,7 +4222,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS | ARM_CP_IO, + .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),