From patchwork Fri Nov 9 17:35:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150691 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp133814ljp; Fri, 9 Nov 2018 09:35:59 -0800 (PST) X-Google-Smtp-Source: AJdET5ckhjaIVNXC89vdODahHKWn+NliLDZVOOMnAQGpz/nG/fE77t9wMbi9afkZKzzfEaHIQRZX X-Received: by 2002:a1c:b7c4:: with SMTP id h187-v6mr238292wmf.70.1541784959050; Fri, 09 Nov 2018 09:35:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541784959; cv=none; d=google.com; s=arc-20160816; b=jzDEK3RvD8iuPTm7shTzLhcaPDYFfxCqoo1AqHe/n3/5hkMKg5t3SOP5ST75ys2FIt I0ANoXNeRkevd9A2SeAbWyNU332o0nK6OBVudzD2Ivj1UksWBTg+sL4vBmYTmPX+ceRW mZPetbK1n9JwPHuBJ5TTMwtFEgLGqdXgnrHA+jnL0/mLQHHUasu73MNi5EwAX5QAKRh1 0C9pnn9Noc1R3k8Tc9A1Lsp0OgimQPSxWc1Oe/3afc7VJNI023hw/n1j0ycNHabCyujR lv3+4fat8ZBZBvsXP6+CbFDdnZlAX47Rykit54B92UCWOVxpMCnxdmB3F2weUx8j95hJ jiLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=TyWQyyFm0+a+PA5xnoBaalY+g39CuNc2keaemJxb6WY=; b=ZKRtuaLSc0eXok4BHzmkqRTNB+pAS2+Si1/yrZG0591/tlVpQRWEbk/MFxBCMaswGA zvKo82K5QcKZpaoewRaGrcIS78Bn5k57pbbdVv+H6hW7gvAQIQVbQpf5ek7CPUM/gimC 5FdZCcwneFgCmmXpN7UMfWtQ0afGmogEjeBHxE2XgA0IgZ3F0HMcw7SRhboVWYn6HPsq QNIseyVl5bUqtXgYIGwlb4dq4COoFJey2mkpUawDIkMFaAMWvBl6lx8pJa8UVL6XpEab 3gEXCFR5+NsOcrFfIb+iqE51zrLy043gcuJHMLq0ITEHS63PeLK/ZaVEJWWNsD3GzS9q 7jeg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id x4-v6si6230246wrw.182.2018.11.09.09.35.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Nov 2018 09:35:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gLAhK-0002tY-FI; Fri, 09 Nov 2018 17:35:58 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" , Adam Lackorzynski Subject: [PATCH 2/2] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature Date: Fri, 9 Nov 2018 17:35:53 +0000 Message-Id: <20181109173553.22341-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109173553.22341-1-peter.maydell@linaro.org> References: <20181109173553.22341-1-peter.maydell@linaro.org> MIME-Version: 1.0 The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented it properly we can enable the feature bit. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.19.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 784a4c2dfcc..b7185234d85 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,6 +1587,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; @@ -1633,6 +1634,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1;