From patchwork Tue Nov 13 15:42:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 150988 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4558879ljp; Tue, 13 Nov 2018 07:50:21 -0800 (PST) X-Google-Smtp-Source: AJdET5c4WdLqKj1Gh8neIdSxsKEY15YubdcikGSXv8p6i6RMXjppI7/yUlH+3uw0L7mRvc9HJNEW X-Received: by 2002:ac8:2b99:: with SMTP id m25mr5438482qtm.36.1542124220902; Tue, 13 Nov 2018 07:50:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542124220; cv=none; d=google.com; s=arc-20160816; b=gw49etmHvXzMbTlRJDeCqy6vu2eFzZx05pUT3Uy3cae2ZaQyY0df/hX5d166C3T88Q ToWhBy1hLQxIAmUYK41efs5Au2Z/nINFUrJ2JbWNnP8Jxr7/qzBtjRRg9Gq+2s89qyOr qqaUKRei1rrFbsggSiuzpttPTsDongzboceTRqVArXugkm0cjmgsJ+qV97j0guMaUWZY YbUxNnqOyq3S3VmptF4mlyafq8VuLtY5q6lijUk5G2OO6lzLc9vf6x3gzLqatSbnIQyn jfIRV6DXEvyERqdqvskMw4s2QvRJrTpxEU+eTe4qc3FMbmvgKsTpgJ8MGEgl5Yh+lxww cidg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=iPkEzaJA7UwFmY3iGx2+gJut9lqK3ams1cmR97ZUHiqQOSLoI7mDHN2ZUXA+SUw4g4 UjW+Wnn3vZrCM0mwVwhy4GYFL+YxlzwuQUiUTPFVzO3GxDUSTGwmBZZ6dN/kp366Sxez zIN+rO2J3LVLCm1bmfVjT0mxrrMCub2whrhDBXTgPI9Wd4BkrvSBKaXn9jguReUFoRdF gr5YFC0fl+mrfY6z+mcE50Ck26BiczGCmfAgRJfny0WmRwDC3CBoMBXfOOp9oTgUeQNu npNkWB4VF1+SUGq2aCWfTc6PG+yWKyr36dgzwpiY+D9uDGnHlY56weS5yfVCIChyvdSE 2nUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GqA3uVk7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 2si3057916qth.155.2018.11.13.07.50.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Nov 2018 07:50:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GqA3uVk7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMaxI-0006Gy-3A for patch@linaro.org; Tue, 13 Nov 2018 10:50:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMar7-0002eK-JM for qemu-devel@nongnu.org; Tue, 13 Nov 2018 10:43:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMar6-0002Yo-Kr for qemu-devel@nongnu.org; Tue, 13 Nov 2018 10:43:57 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51265) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMar6-0002FF-DK for qemu-devel@nongnu.org; Tue, 13 Nov 2018 10:43:56 -0500 Received: by mail-wm1-x342.google.com with SMTP id w7-v6so12402895wmc.1 for ; Tue, 13 Nov 2018 07:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=GqA3uVk7k+oZ4dkSt8E0OsPLnFa4USOUakEwEIu+U3j70dg0/eXEK+Ewcr7MS+MorW dZlWiYHuCqsypym/Xbw2Igh/ZU55EwczfH2VchNx1avVDqtuJZc4S80GVD5sdafPiP9X +Wp6f7KHr9qvicjjkaLjbBJZFN+y8CNy4+2AM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=kOEBnu80cUVRl2YA7x6Mwm8jSTtcpPHZDWd8S4zNPx5iPrHjCevBIQWH78W5RHXlGA IquEirS5aDOalll0MByUXjOtz8hgZNC3rrTuSVFmHa/DYDtOkz721Z1QQKNjxqciWkI5 +10Bw8w4vlfWsAWuFdKhgAkp2KQC/IEtsciyIuPoVx/3xHRkStRv2AZH/wmKx1nykApd h3NIETrG2nN//pOheNsIeAQOu6KlsnCsnIasiM1uCzDLPoLqS9hDwRoF5krSfQuZQQnh rAgnhBZrBQ4qry4AvReyNdac2KyGTNQ8LfDtM3WS/k9hMvu+dgaOVuVaxHUG/PE3HzKF MkLw== X-Gm-Message-State: AGRZ1gItRs/CjkFnHYz2l90r1Q0YbIeIiR4OQLE9EP8vtpX3u35yiWy7 UZMdmtBcGNXTk25TgRho81mbs5eKiV3BSg== X-Received: by 2002:a7b:cd97:: with SMTP id y23mr2406905wmj.129.1542123801311; Tue, 13 Nov 2018 07:43:21 -0800 (PST) Received: from cloudburst.twiddle.net (26.red-176-87-105.dynamicip.rima-tde.net. [176.87.105.26]) by smtp.gmail.com with ESMTPSA id s16sm3479709wrt.77.2018.11.13.07.43.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 07:43:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 16:42:26 +0100 Message-Id: <20181113154226.14396-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113154226.14396-1-richard.henderson@linaro.org> References: <20181113154226.14396-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v4 4/4] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) -- 2.17.2 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bc0badf53d..bd51eb43c8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * and then query that CPU for the relevant ID registers. */ int err = 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features = 0; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,39 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); - err |= read_sys_reg32(fdarray[2], &mvfr1, + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7))) { + /* + * Older kernels don't support reading ID_ISAR6. This register was + * only introduced in ARMv8, so we can assume that it is zero on a + * CPU that a kernel this old is running on. + */ + ahcf->isar.id_isar6 = 0; + } + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migration. + */ kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -95,13 +125,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) if (extract32(id_pfr0, 12, 4) == 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); }