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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id a2-v6si3299975yba.55.2018.11.23.07.11.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 07:11:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NMrK4yOj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQD7D-0007jh-1r for patch@linaro.org; Fri, 23 Nov 2018 10:11:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCj6-0000Hi-RH for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCj4-0003le-QU for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:35 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37567) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCj4-0003kD-IY for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:34 -0500 Received: by mail-wr1-x444.google.com with SMTP id j10so12586691wru.4 for ; Fri, 23 Nov 2018 06:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rRT9/p5Z5WH4Z+cvxcGe8HvxMvUgIXvOL8XKXtOdL3Q=; b=NMrK4yOjLkiSLE8TME8a3eXKO3wvsG2NKYSed76gz+LY0Wgy0FYRkGT/LtXsu3TCzw UFF1MxZ/UCPXZayKUwFA9ghpt0jXmf2WdcFn4wYL/JohGFva9LppwUeKj+9dg3ganEVz 1Z9/xWV1wQwKbfWsRTayc4ZEbeyZSa+rsUcm0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rRT9/p5Z5WH4Z+cvxcGe8HvxMvUgIXvOL8XKXtOdL3Q=; b=Ym6PfzApAuFeceUJHglleYjeZXLHgRRd1VeP7Fx3oaJ95jG9IwH04kKarllhp3OdaG wZO1/JZqx1V8L+MNqiQV7VVP6WNnowzphx16zWKN7I/6SEMQzUhhHdn3hdKYKc3McKS9 OsuDu4aQKdnkkICEpHSiGldo34u/ZyJNwVXkq4YwtSolZ6Pbu+uT2gx5uXHZmEBzbdYU X0LJ85fibLJ2SAIGFv8ayvF33nTAVn2URTzqxP9kJVQB2utjxn0akAfPgmv3CYaAY4Ez F92sn7NlbVSRonezt6hTnTZg14+i7TdrSP+qlUMQsw2cT8CQO5xJ90nlxoJg+7cabpzY sdeQ== X-Gm-Message-State: AA+aEWbp82PA9VGm1u2/mYxV91383nnbhETV3q6mS0D26OalKEHNUcit 5RHPOa/5HuS2OVpdXHwP57lv90jqGvL0bg== X-Received: by 2002:adf:d0c9:: with SMTP id z9mr13797760wrh.317.1542984393079; Fri, 23 Nov 2018 06:46:33 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:55 +0100 Message-Id: <20181123144558.5048-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.0 v2 34/37] tcg/i386: Restrict user-only qemu_st_i32 values to q-regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is one more step toward the removal of all scratch registers during user-only guest memory operations. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5cad31cfe5..79de8d0cd2 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -240,7 +240,17 @@ static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) #else static const char *constrain_memop_arg(QemuMemArgType type, bool is_64, int hi) { - return "L"; + if (TCG_TARGET_REG_BITS == 64) { + /* Temps are still needed for guest_base && !guest_base_flags. */ + return "L"; + } else if (type == ARG_STVAL && !is_64) { + /* Byte stores must happen from q-regs. Because of this, we must + * constrain all INDEX_op_qemu_st_i32 to use q-regs. + */ + return "q"; + } else { + return "r"; + } } #endif /* CONFIG_SOFTMMU */ @@ -2038,15 +2048,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, switch (memop & MO_SIZE) { case MO_8: - /* - * In 32-bit mode, 8-bit stores can only happen from [abcd]x. - * ??? Adjust constraints such that this is is forced, then - * we won't need a scratch at all for user-only. - */ - if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo = scratch; - } + /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, ofs); break;