From patchwork Tue Dec 4 13:29:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 152813 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp8069307ljp; Tue, 4 Dec 2018 05:29:56 -0800 (PST) X-Google-Smtp-Source: AFSGD/VgTKPRUANMSU5D+atnaD68R2vfXJD5jv6kNosIF8dN/77vDicY940tOV6oEXK4Qp6vM6p5 X-Received: by 2002:adf:8464:: with SMTP id 91mr19123371wrf.251.1543930196263; Tue, 04 Dec 2018 05:29:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543930196; cv=none; d=google.com; s=arc-20160816; b=JbQPij+l7boXqv+ZoySz7IknjgIcAjExHEP9f6qqEO+5K40j+IuGUT/ic8+EOXtRzz 2mQF4x8xhM6Jdsk9S8mu//UvQDodOaJTJtlF6BNr+i0PSDHfZCkY4FBPbHWBgM/AFT7x MWuRqLfnLfcsCvLde48oYZkb6+iAgT1AexYMJl4BbTosMnUXH/XKD1UPLi/2gxlbJLxJ Ks1KiYMAx9X+gjVsiUheKnYCnhEd1ixCQldcmDntdch9AV6NjKGzjp+HGNx59ACOp0sa WbM3D8NaEsGkvztHIwatAnMhre42P6JFb5umewW6d0P1YMmVDoOjLeKtDrXPnA8PZZbe wmgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=5ODWp/MEZ7MIgMwbY8al9xKiOHBbFkpkw8heg21DcHc=; b=jK1Tx6125mlWhbQnncu/qJxGVMhQdchAhp6q5PUrH68KMhkf2fVqw5egxwpN9ztOUl TWjs7HpBRxTJmtOOlGzZ1O2NLmc0UfDcKp6LB6IRKOWvCDXQO0nydslkKiP6/zKCK9MP BtS8FJPPJeA1vuJeGSOPPqCwzZJQVJgRlYdxEt2B4vk33Z4tm31b994oIyccKHkZwosv tFV4cXMKz5E+atf/bnu73IA5BFMfVZq7dvP7AnhzA1oD67Xe3OaFPu67Cl14QWkDOlOG gJHOHDS/vtaHrN0kxPBtIlHmSgP44+hwq/ITJTT48B20MlRgPRUyFVwaGR763zaCQe/m 31JQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j204si8465962wma.169.2018.12.04.05.29.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Dec 2018 05:29:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gUAlv-0008Cn-QU; Tue, 04 Dec 2018 13:29:55 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 5/5] target/arm: Create timers in realize, not init Date: Tue, 4 Dec 2018 13:29:52 +0000 Message-Id: <20181204132952.2601-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204132952.2601-1-peter.maydell@linaro.org> References: <20181204132952.2601-1-peter.maydell@linaro.org> MIME-Version: 1.0 The timer_new() function allocates memory; this means that if we call it in the CPU's init method we would need to provide an instance_finalize method to free it. Defer the timer creation to the realize function instead. This fixes a memory leak spotted by clang LeakSanitizer when a CPU object is created for introspection. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.19.2 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b84a6c0e678..0e7138c9bfb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -679,14 +679,6 @@ static void arm_cpu_initfn(Object *obj) qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } - cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, - arm_gt_stimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); @@ -882,6 +874,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } } + + cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_stimer_cb, cpu); #endif cpu_exec_realizefn(cs, &local_err);