From patchwork Thu Dec 13 11:55:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 153636 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp708675ljp; Thu, 13 Dec 2018 03:57:33 -0800 (PST) X-Google-Smtp-Source: AFSGD/VZ12THJYBVp49bqP9nuYDD/i6p69katVhUIlespoNZ4a2ZfSqJubvlgkWh6JBYco/TyCRZ X-Received: by 2002:ac8:4294:: with SMTP id o20mr23993128qtl.118.1544702253364; Thu, 13 Dec 2018 03:57:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544702253; cv=none; d=google.com; s=arc-20160816; b=xkBkLL9EsVjVDkhqYRCQktg3pf64bBMgxDe9K2BqZgPJt4nYx0AQsHbQT9Mo8pq1Nm HFqE2eSh8OktJMJnsaU+Qg/TVmKnTNCsFWOgy0DCb18feQVBpnjrTDg0yV6s/2nHNwQD GDyULQaR9u4PIYw288rt7f1Xk7a9ZOv6l2aM1g0KWF981mnvQrmynBbA0+U/gP/qoWwJ q01EFhaq2MX2x/d6Oqfh31Wq3KyMuVBfWI5be+V38gsipKXm86uG5MvLk8J7NUZtN7Rb ZIxbxWjL0nBzi9T2BkGdnY1d2zJyQQY0ZFh6hEQh3UmarAhsfGOrFON24/bitRTbCzxn jSPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ekMfKo3ZA6YOlbMnD8F8r3Cf15l5nuMJM++IxWwQXiA=; b=eFhr2AZzC/9aeLaYRRMEAxOzPcowDee3KKRfZKnePe2xcKayFFtfxvT6aKVXPWeeBv iKX23lhuMPr0NZrP/DIkjsWCrE0YFMC4A1nPy2Ax6/ToPVKF+OAnQe5dkYVx3Lfts8Y5 xzJJ6boxnkGQMVmw84tKFN1KRH72R55P+LUEt5c8fFKZUwGIvTpwdTechaHIu4HJXFBs qs6MiLPdVN2QJ7DcAdMwFAhPiQSAVxFzR286P69zBDY/ViXE9gsDLGYvR3AiRUaQWdg3 NBEPnDy5qzEmF9jsR2oGT4PflyqzLJLEHIKACzpdnVGTB7nLOgwEZB7H0PauXKUNKdLU YJfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHqBUJQp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r30si928334qtd.209.2018.12.13.03.57.33 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 03:57:33 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LHqBUJQp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51925 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPcS-0000lY-Th for patch@linaro.org; Thu, 13 Dec 2018 06:57:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXPaB-0007dV-TW for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXPa8-00008H-6B for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:11 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37550) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXPa7-00007N-6q for qemu-devel@nongnu.org; Thu, 13 Dec 2018 06:55:07 -0500 Received: by mail-wm1-x342.google.com with SMTP id g67so2091756wmd.2 for ; Thu, 13 Dec 2018 03:55:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ekMfKo3ZA6YOlbMnD8F8r3Cf15l5nuMJM++IxWwQXiA=; b=LHqBUJQpc+kgMPo+3cbVB81x78OGSqdD07GFNZDNxvZ7yh+Q+J09iCAgETHjVD0bOo RU04Y0n1rRWKMeogvvv+4qIO1bdClFqI1hltmZdVVCnM4hyTDZ0kPkWyMQFb7qXbdm3Q U4bI+B0jgwjZ7aExf7rg7A1uOxdpF+wTBrApw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ekMfKo3ZA6YOlbMnD8F8r3Cf15l5nuMJM++IxWwQXiA=; b=i9D/Iayt+3XNcoWLA8yPoDPmxdwi/1mpEd+zOjhi5K7dOQZYNHIJqfNQRsf67KhUio ha10+5JlI3j9VkaSxejoXU1DuqLmWORrMN/4gABLvi8ksuk+EqVl+A3L3rr2HL94K3im VKce6TU1fdvloGIGBHt6aCJjJOyqQwFxccaf7qqdNH2lYzYZm8zU4cq//XhIwDNw66oC qsY3hOq1r9F/ZshTr+E4vrrBP9w6nuOLYq3AtPrra7Fip6sEW5JfDjEU4v0o/BSAAdnP SqhahW02MoElpbspKFJsoWrysHqBmQUz6wPljRGdwMBFfUBdh8i1B0SM1FJTScjNxYQ2 bILw== X-Gm-Message-State: AA+aEWYhzdVN7KlbizPNHm1UxU9va7ZXp+l/CytLjKR9Ui3Z4ymSWn/T PdoXR/OG/zu/K5WQ6qWZsWpQAQ== X-Received: by 2002:a1c:35ca:: with SMTP id c193mr9697688wma.146.1544702106109; Thu, 13 Dec 2018 03:55:06 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g201sm1255645wme.43.2018.12.13.03.55.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 03:55:04 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 9997A3E0363; Thu, 13 Dec 2018 11:55:03 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 11:55:03 +0000 Message-Id: <20181213115503.24188-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181213115503.24188-1-alex.bennee@linaro.org> References: <20181213115503.24188-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v1 2/2] target/arm: defer setting up of aarch64 gdb until arm_cpu_realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Peter Maydell , Omair Javaid , ard.biesheuvel@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If we setup earlier we miss the parsing of the aarch64 state of the CPU. If the user has booted up with: qemu-system-aarch64 -cpu host,aarch64=off -enable-kvm we end up presenting an aarch64 view of the world via the gdbstub and hilarity ensues. Reported-by: Ard Biesheuvel Signed-off-by: Alex Bennée Cc: Omair Javaid --- include/hw/arm/arm.h | 2 ++ target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 20 +++++++++++++++----- 3 files changed, 21 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index ffed39252d..f9a7a6e2fb 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -171,4 +171,6 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, ticks. */ extern int system_clock_scale; +void arm_cpu_enable_aarch64_gdbstub(CPUClass *cc); + #endif /* HW_ARM_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..100a72ff81 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -890,9 +890,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. */ +#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + CPUClass *cc = CPU_GET_CLASS(cs); no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); + arm_cpu_enable_aarch64_gdbstub(cc); } +#endif if (arm_feature(env, ARM_FEATURE_V7VE)) { /* v7 Virtualization Extensions. In real hardware this implies diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..53cde60557 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -434,12 +434,14 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) return g_strdup("aarch64"); } -static void aarch64_cpu_class_init(ObjectClass *oc, void *data) -{ - CPUClass *cc = CPU_CLASS(oc); +/* + * We can only setup aarch64 gdb support once we realize the CPU + * object and know what mode it has been booted in. This is called + * from arm_cpu_realize. + */ - cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; - cc->set_pc = aarch64_cpu_set_pc; +void arm_cpu_enable_aarch64_gdbstub(CPUClass *cc) +{ cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; @@ -447,6 +449,14 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_arch_name = aarch64_gdb_arch_name; } +static void aarch64_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + + cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; + cc->set_pc = aarch64_cpu_set_pc; +} + static void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = {