From patchwork Fri Dec 14 05:23:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153749 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1676430ljp; Thu, 13 Dec 2018 21:33:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/WaIQwZEJbmlcxyqRVjrk97ypx4q+dcyJeUaMo4IxRQTx7vJMVc7G0KTOXmsCsS+OfjCbm6 X-Received: by 2002:a37:c3c3:: with SMTP id r64mr1416478qkl.70.1544765618941; Thu, 13 Dec 2018 21:33:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765618; cv=none; d=google.com; s=arc-20160816; b=LZUBJ3CLOGiWf/EGOkVaKLPl1VS4lmfWCL6ST2AG+/X5aUACxlAPWKTWZge20YmCYt b35A1IwCy7WzqpKM2m1zByXoFc+CcyAX9GAF/IK/OOsCJrexPZLSelPA0Pj4yEBlDVDJ fLX0DHjCvsSwEqaMjsjsafs4v7s3r/gvwZ/KbZ+3L1lK1FRowuxXOFTF+AK56K8waSWr H8SJtvTOaV8CHZSDCRD9kU0Zu7mnAOtR6nUghAwecBMjM/lqAVObb9Mj+T2M395pGvRE ls/gYScTARniFS1gicDuom9ng2WCIp+kKSfDzBWE/e3IAU9DV4GZjwnHLKH4ErdbkBsr Aatg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AUMg+u27uMOuJ6XW+OsUe7C34ZHfjbNbRhgYaArpPkM=; b=BnvvGpICuxZCljj9suki5VZq7Hm9PI6pjI3UszmuysztqtZtbu7Bt3L+Vx1rCiJsRO hYS5FJYEPUegabj55vZNjO7Cf3hgYjwI+Y0G68zwihrwYVHE+dTg96VKQMvGXW8EkHbD NBfVoqKYLLPF3ccurqXFH3FWF0ttWm06NSC22nLgDii7rmEEwSiDl4S5Nq1nBoKb9FM4 YifyJkCFxmZ9nPg93eTL8oGIn100owu1wRgrCOhhKtEUFmis/fL04vNgh0+1TcjwWact MhrjWPuHmTMGWIKXaW5ifM9BMlzTWy7hWcUu4kZ3WLasDE11KNayMr02dS7DPoJ2j25k 0cTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BrZ00UN0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o44si1377011qve.201.2018.12.13.21.33.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:33:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BrZ00UN0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59469 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXg6U-0002mk-Av for patch@linaro.org; Fri, 14 Dec 2018 00:33:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxi-0004TP-Fh for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxe-0005QF-Ct for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:32 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:37726) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxe-0005Q1-6c for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:30 -0500 Received: by mail-oi1-x241.google.com with SMTP id y23so3631501oia.4 for ; Thu, 13 Dec 2018 21:24:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AUMg+u27uMOuJ6XW+OsUe7C34ZHfjbNbRhgYaArpPkM=; b=BrZ00UN0vRm58yHg38v6IytT1EKGv1JUjTjDDmbGsCNanAEOr8Ur41MBiyx4KY97QP z4RReDOJPQPsozSKk8OfStxjiAZjr/KAcPLJl3tAlg/9REXFKrPQjPJrYYuZsAYfdyxM k8eo9JdqINMO7c8jy7SDWvneT4VPoWQN0mdQY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AUMg+u27uMOuJ6XW+OsUe7C34ZHfjbNbRhgYaArpPkM=; b=FnV1PvkviGtQUkK90bOP2jb6ny0RMxkBhjJRo/RDtAP0ESTnkXCQ0wUIuuo2vwk7l8 lp6XNChPqwkqZ2POieOCj6mLkSriEsKvoi6z5EpHrZHB+tnQoYJNLmjyI/JsIc6s3m+V O1ipI3tRIMCl2IQbe1uuSfAIVwflNnpEwqfBq4QP725uXSEdzEQCqttIwYwhcRBnQTpc 9rl/5bIC6pDkFpttlwPk8xYKFbpQ+Cd5xbp9pltsA6nAEhjd5H4yZcRlUE+ekgIE20OP hWsZ3T9oWKQsu+eGZjH4uzS914+NEoR4u/tDa6Kuu/LCxZgnyYP46Sk5LhwqV1fmskKa q46w== X-Gm-Message-State: AA+aEWZfUSFEdCnw1giOA90dUyjwDNi7w/LfGQyCRAQCF8GkkjujDhM0 m3451BL9LjWZopmADrLRbrl39vDbiNjxGA== X-Received: by 2002:aca:4d47:: with SMTP id a68mr930371oib.43.1544765069266; Thu, 13 Dec 2018 21:24:29 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:57 -0600 Message-Id: <20181214052410.11863-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 14/27] target/arm: Move cpu_mmu_index out of line X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is, or will shortly become, too big to inline. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 48 +++++---------------------------------------- target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 43 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 898243c93e..6435997111 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2739,54 +2739,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } /* Return the MMU index for a v7M CPU in the specified security and - * privilege state + * privilege state. */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, - bool priv) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv); /* Return the MMU index for a v7M CPU in the specified security state */ -static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, - bool secstate) -{ - bool priv = arm_current_el(env) != 0; - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); /* Determine the current mmu_idx to use for normal loads/stores */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - int el = arm_current_el(env); - - if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); - } - - if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); - } - return el; -} +int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ typedef enum ARMASIdx { diff --git a/target/arm/helper.c b/target/arm/helper.c index bd0cff5c27..56960411e3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_current_el(env) != 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el = arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) {