From patchwork Fri Dec 14 05:23:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153757 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1679785ljp; Thu, 13 Dec 2018 21:39:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/XKATOzWzCwKv52slv115wu3D3WG0ynkmgeXICHEcsDsGq0IeWGnrSzHoQNDLheTP+xadAq X-Received: by 2002:a37:ba06:: with SMTP id k6mr1394131qkf.115.1544765964525; Thu, 13 Dec 2018 21:39:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544765964; cv=none; d=google.com; s=arc-20160816; b=UYYTCsLLg78DwXGYtQEd+CT5tVvh3fyWDnzpSeM6aJ0d4PXFbojammOhvia6/Pb+w2 rcoTsszTakdZX/vl34Dqwg+m/RaOldVUGU+q/o5U+yNpsNs4U/5zgItTvBUWpGOywl1n ZBtt67wugt0Df1EADx+NYIjCKv4K+7qXI2+bdOIXtBeid3fJPCJsjspvbp4SZ7kulb3Z ztbhzdGK+Dxt3Ty4THiAtxF/vDhDNIDq3mAJr2Q+c+pZvxy9nDDKxLKo83vPniILHvoK XUkg2TjynUs5sDhp8ghVzbJR8J6cO4SjznZ2lI87Aubw43k7c2Q6deYfSJmKykgsgMYH lEqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pYcny5cc3WX0BfamIQvSjkTSyzc+7TQPjBPr3uGgHBQ=; b=HnAA4FWw0QfJmyfmY/Z+ardsIkjyGxSm5TDckduNdkyyo4T+f8h042rVgPRtHpanoL Tp3P5ZQehMUInK7gmtzcHEL7NE3sbuAdHsYqSILhwE7415fFWLRf9+P7DhWfFb7gwjhL GC13FmDgwW/BRqWv7JiNYgLg+mb73Hxcs71dLpvSCC8Oa5i7OOgprnbbkl8B+f+bR0YU GyRLQIhHXDAbGuTRx+NMQhr6RHkRoYOpU+QmLlVqDtroH+I0z1k+K4NKkN1oHtG6okhU heBzTeNDLIpgk26XMgmBkpkaATPrjOWeMgs71mnKYj3mIisYfby39k+aEadACRZKF6i4 r8iQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J0jkBQvr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y7si2250414qkc.188.2018.12.13.21.39.24 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 13 Dec 2018 21:39:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J0jkBQvr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXgC4-0008I8-0b for patch@linaro.org; Fri, 14 Dec 2018 00:39:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55790) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gXfxk-0004Vs-JZ for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gXfxi-0005Rj-5Z for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:36 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:45885) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gXfxf-0005Qx-Aa for qemu-devel@nongnu.org; Fri, 14 Dec 2018 00:24:32 -0500 Received: by mail-ot1-x344.google.com with SMTP id 32so4274401ota.12 for ; Thu, 13 Dec 2018 21:24:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pYcny5cc3WX0BfamIQvSjkTSyzc+7TQPjBPr3uGgHBQ=; b=J0jkBQvraRMoiUGiJ20StbFewx56pe1nrduyGU+LpuGE+6IIo8/YqFW15MPH+anDFe RjqcACMUeEwvzpd6gc0g4ul77SXlcBjbAOAf79ECJaBBHmD5uut+4Yqo7YvFbn4k4Vzj EVcZ8/l6LzbYgT3iYItkz7D1aGoL/lgwmPWCg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pYcny5cc3WX0BfamIQvSjkTSyzc+7TQPjBPr3uGgHBQ=; b=qhgK3tYVQ5VX5R+6oSapdQf6N7+6RmOe2pizSyOlmPcvKQTDTRhQzv1rJlFQpkWr6S 15bYaF1qUnLll+cIyCXEMOHBXGPy/ml7H0xEwdUud7YSFyqAHMm2lw1AwcqhCY+w+7/I ELKqn5KDCeSsoOnS+FaG3M7eLNp0az+/sJEfIzeZPQ7rAii7d3F8B95L3yRj6UDfwyOq WKvxJjWLBZ/mVTo3uTP5RGy8NATAwJR1q1Md2S42wvRpCdsYYcanwMLP38ASDRoRyv/K 7vLbD9iD/0POFaHkkbS8Ukkl3MH66FzetimDmwiVVdgRXI17Zuse++TpYRJd7SV34j95 dDdg== X-Gm-Message-State: AA+aEWbwokgo+YEObqrTLcJJn37NYLsdgbB9iwu6LoEwDQlGcVPUp4le OJXg+1RUUxL43yj24NK46R4Blueo04SIDA== X-Received: by 2002:a9d:12f1:: with SMTP id g104mr1124052otg.22.1544765070327; Thu, 13 Dec 2018 21:24:30 -0800 (PST) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id r1sm1845379oti.44.2018.12.13.21.24.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 21:24:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:58 -0600 Message-Id: <20181214052410.11863-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pattern ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson ---- v2: Move arm_mmu_idx declaration to internals.h. --- target/arm/cpu.h | 9 ++++++++- target/arm/internals.h | 8 ++++++++ target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 32 insertions(+), 12 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6435997111..3cc7a069ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2747,7 +2747,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); -/* Determine the current mmu_idx to use for normal loads/stores */ +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ int cpu_mmu_index(CPUARMState *env, bool ifetch); /* Indexes used when registering address spaces with cpu_address_space_init */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 6bc0daf560..4a52fe58b6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -912,4 +912,12 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx: + * @env: The cpu environment + * + * Return the full ARMMMUIdx for the current translation regime. + */ +ARMMMUIdx arm_mmu_idx(CPUARMState *env); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 56960411e3..50c1db16dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, limit = env->v7m.msplim[M_REG_S]; } } else { - mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + mmu_idx = arm_mmu_idx(env); frame_sp_p = &env->regs[13]; limit = v7m_sp_limit(env); } @@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu) CPUARMState *env = &cpu->env; uint32_t xpsr = xpsr_read(env); uint32_t frameptr = env->regs[13]; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); /* Align stack pointer if the guest wants that */ if ((frameptr & 4) && @@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, int prot; bool ret; ARMMMUFaultInfo fi = {}; - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); *attrs = (MemTxAttrs) {}; @@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } -int cpu_mmu_index(CPUARMState *env, bool ifetch) +ARMMMUIdx arm_mmu_idx(CPUARMState *env) { - int el = arm_current_el(env); + int el; if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - - return arm_to_core_mmu_idx(mmu_idx); + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } + el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + return ARMMMUIdx_S1SE0 + el; + } else { + return ARMMMUIdx_S12NSE0 + el; } - return el; +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return arm_to_core_mmu_idx(arm_mmu_idx(env)); } void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); uint32_t flags;