[PULL,24/42] disas/microblaze: Remove unused REG_SP macro

Message ID	20181225205529.10874-25-richard.henderson@linaro.org
State	Accepted
Commit	11cee55f18a02637945f12718237506abb8073b2
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:55:11 +1100 Message-Id: <20181225205529.10874-25-richard.henderson@linaro.org> In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg queued patches \| expand [PULL,00/42] tcg queued patches [PULL,01/42] elf.h: Add the RISCV ELF magic numbers [PULL,02/42] linux-user: Add host dependency for RISC-V 32-bit [PULL,03/42] linux-user: Add host dependency for RISC-V 64-bit [PULL,04/42] exec: Add RISC-V GCC poison macro [PULL,05/42] tcg/riscv: Add the tcg-target.h file [PULL,06/42] tcg/riscv: Add the tcg target registers [PULL,07/42] tcg/riscv: Add support for the constraints [PULL,08/42] tcg/riscv: Add the immediate encoders [PULL,09/42] tcg/riscv: Add the instruction emitters [PULL,10/42] tcg/riscv: Add the relocation functions [PULL,11/42] tcg/riscv: Add the mov and movi instruction [PULL,12/42] tcg/riscv: Add the extract instructions [PULL,13/42] tcg/riscv: Add the out load and store instructions [PULL,14/42] tcg/riscv: Add the add2 and sub2 instructions [PULL,15/42] tcg/riscv: Add branch and jump instructions [PULL,16/42] tcg/riscv: Add slowpath load and store instructions [PULL,17/42] tcg/riscv: Add direct load and store instructions [PULL,18/42] tcg/riscv: Add the out op decoder [PULL,19/42] tcg/riscv: Add the prologue generation and register the JIT [PULL,20/42] tcg/riscv: Add the target init code [PULL,21/42] tcg: Add RISC-V cpu signal handler [PULL,22/42] disas: Add RISC-V support [PULL,23/42] configure: Add support for building RISC-V host [PULL,24/42] disas/microblaze: Remove unused REG_SP macro [PULL,25/42] linux-user: Add safe_syscall for riscv64 host [PULL,26/42] tcg: Renumber TCG_CALL_* flags [PULL,27/42] tcg: Add TCG_CALL_NO_RETURN [PULL,28/42] tcg: Reference count labels [PULL,29/42] tcg: Add reachable_code_pass [PULL,30/42] tcg: Add preferred_reg argument to tcg_reg_alloc [PULL,31/42] tcg: Add preferred_reg argument to temp_load [PULL,32/42] tcg: Add preferred_reg argument to temp_sync [PULL,33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi [PULL,34/42] tcg: Add output_pref to TCGOp [PULL,35/42] tcg: Improve register allocation for matching constraints [PULL,36/42] tcg: Dump register preference info with liveness [PULL,37/42] tcg: Reindent parts of liveness_pass_1 [PULL,38/42] tcg: Rename and adjust liveness_pass_1 helpers [PULL,39/42] tcg: Split out more subroutines from liveness_pass_1 [PULL,40/42] tcg: Add TCG_OPF_BB_EXIT [PULL,41/42] tcg: Record register preferences during liveness [PULL,42/42] tcg: Improve call argument loading

Message ID

20181225205529.10874-25-richard.henderson@linaro.org

State

Accepted

Commit

11cee55f18a02637945f12718237506abb8073b2

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Wed, 26 Dec 2018 07:55:11 +1100
Message-Id: <20181225205529.10874-25-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP
	macro
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

tcg queued patches | expand

Commit Message

Richard Henderson Dec. 25, 2018, 8:55 p.m. UTC

This causes a build error with debian sid, riscv64 host:

disas/microblaze.c:179: error: "REG_SP" redefined [-Werror]
 #define REG_SP  1 /* stack pointer */

In file included from /usr/include/signal.h:306,
                 from include/qemu/osdep.h:101,
                 from disas/microblaze.c:36:
/usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition
 # define REG_SP 2

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 disas/microblaze.c | 1 -
 1 file changed, 1 deletion(-)

-- 
2.17.2

diff --git a/disas/microblaze.c b/disas/microblaze.c
index 598ecbc89d..c23605043a 100644
--- a/disas/microblaze.c
+++ b/disas/microblaze.c
@@ -176,7 +176,6 @@  enum microblaze_instr_type {
 #define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
 
 /* alternate names for gen purpose regs */
-#define REG_SP  1 /* stack pointer */
 #define REG_ROSDP 2 /* read-only small data pointer */
 #define REG_RWSDP 13 /* read-write small data pointer */

[PULL,24/42] disas/microblaze: Remove unused REG_SP macro

Commit Message

Patch