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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id h74sm140934699pfd.35.2019.01.10.04.17.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:17:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:17:26 +1100 Message-Id: <20190110121736.23448-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110121736.23448-1-richard.henderson@linaro.org> References: <20190110121736.23448-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 01/11] target/arm: Introduce isar_feature_aa64_bti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also create field definitions for id_aa64pfr1 from ARMv8.5. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8512ca3552..fadb74d9a6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1630,6 +1630,9 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SBSS, 4, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) @@ -3268,6 +3271,11 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */