From patchwork Fri Jan 18 14:57:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 155979 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3386645jaa; Fri, 18 Jan 2019 07:30:41 -0800 (PST) X-Google-Smtp-Source: ALg8bN72q3YaNLKUVQ/BhaW0ENFJ7rM4gaFbpRxlTSb1XK/8+Ti2uJe9XkSMu+SUEyTBKLVPdowA X-Received: by 2002:adf:f903:: with SMTP id b3mr17759125wrr.82.1547825441727; Fri, 18 Jan 2019 07:30:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547825441; cv=none; d=google.com; s=arc-20160816; b=X+8GZdNoE/hJk+R7X+md1iCRTA6QZs7D3lg6qDmtLF3BDiki06nGk/4SJaYPNGAPnM P4z/NTHw8CxtBgliNz7Q0x7tQT+edZjvm4aA/b691/AfJg37N7FrP4w1ie35z7aMErQd +DM8r1o27srQlm+Tf6IXO568ivbw1oNGJUNsFqN0y0clt9sjDvxG/FMAqhdj1g3qbxZ7 1UhuyDwY1J9VA1FBxWDYpONAdQxVYGHAShq2JB0pN9Rh61/5Fe5axzE/Ndt31V3Ii5n1 Rkk5UHA0NLu++d5F08+i78ZKO8zZHVvKy5W9VU1OVFFJQX+up5SToYllmR1pZxrSD2qe 4+Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hq4QS5RPobZeGpNsDMA6FS3mXhorl1b6YwcgrpD/q/I=; b=Kd+flABWya64k/NZ95J6eRDKe1PwVK9qcA4YSo3cJwpbUUZYBYuQJxMXOgAJPDdxZy 2AnGP/cfzh/u21Jw3DuC5XjtsIUtEHc4/etQA5TC+Irj/QK1GqtBtMUjxX2tMzQRmHya 24ohXD4A4LaQ2zvkwgX1Lx+wpy5BvWNsg2KLgMwmquLqvq5dJ4DkKnK1YEcQmSzJvO6O mn8sCTAtUa4TXTrIE+0ZfTE4/7FJy7HWRiGDXaAZ7T//SQEO7mx04XAphIFzG2g0Gg7G RI/1S5FIepahxInJqlxbXAzRc96RQtfs7YQIHQCcsLXw1B7rY+g6BCzLER3001bLnFOk nHuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TWidqEle; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f10si59019418wrq.38.2019.01.18.07.30.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 18 Jan 2019 07:30:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TWidqEle; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:41501 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkW6S-0004pb-IT for patch@linaro.org; Fri, 18 Jan 2019 10:30:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43292) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVbg-00030o-T4 for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkVbf-0007ah-UR for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:52 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gkVbf-0007Zr-OS for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:51 -0500 Received: by mail-wr1-x431.google.com with SMTP id 96so15448449wrb.2 for ; Fri, 18 Jan 2019 06:58:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hq4QS5RPobZeGpNsDMA6FS3mXhorl1b6YwcgrpD/q/I=; b=TWidqEleIAG3J9f2GV+T8CRI7wMPIKMiFZN2itJoKOvPtVANyPqAghgzcEzuYtLX2l v+GfTTorYnIvyuIdeLVM4xCES1XlI86VnSpkqIzXFiyBOGv6VEjy6QjpEgs7dUy7LHIW iyQVeqpIvXFUtf8bF3YtutUCLgKhBXUIpqt8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hq4QS5RPobZeGpNsDMA6FS3mXhorl1b6YwcgrpD/q/I=; b=gWHigj/EV7PwMJH87xomEUttMDNALR+eQptO7bxAu4cOi4+hn32SXEvu+nXoyXl8qh +whWb+ZmOHmGh5PcWzVWrK+iD3vUgudYfDRMcD/JXkfunCc5YHloWSFrhYmK2W98cSZf Gf+wxrUH4hZlX6cNs7ZulGsJDQv30+zau4frfo4nIR7Q18Qu9XuDyKyYTHonoUWEtTu1 LC56GE2CmJlZSQW85HM5o3uaVGJb9PAmrb05OBNeRuxJTkl5EhS6W42dYZIsKsWN6l2U zJ+LMuqgVFlVFd+rtuS8WEhekZBXYrXMKyRdCoTiru6Kv/tx4zYjl1W+b9WQ3IGsVD5i kdPQ== X-Gm-Message-State: AJcUukcywZ6rUyn1ywEjkCBFlY+3/+1d6y2k6oX6FEaP1+QsDiTDbqi+ DKh9F6iBy0X6eYiMKy4OX0H0XjKi1D+iSQ== X-Received: by 2002:adf:fe8f:: with SMTP id l15mr2053255wrr.313.1547823530447; Fri, 18 Jan 2019 06:58:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:54 +0000 Message-Id: <20190118145805.6852-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 Subject: [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Aaron Lindsay Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- target/arm/machine.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c49e0d70cbb..733cfdc5a0f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1459,11 +1459,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, .access = PL0_RW, .accessfn = pmreg_access_ccntr, .type = ARM_CP_IO, - .readfn = pmccntr_read, .writefn = pmccntr_write, }, + .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), + .readfn = pmccntr_read, .writefn = pmccntr_write, + .raw_readfn = raw_read, .raw_writefn = raw_write, }, #endif { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, - .writefn = pmccfiltr_write, + .writefn = pmccfiltr_write, .raw_writefn = raw_write, .access = PL0_RW, .accessfn = pmreg_access, .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), diff --git a/target/arm/machine.c b/target/arm/machine.c index 7a22ebc2098..b2925496148 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu = opaque; + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ @@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque) return 0; } +static int cpu_post_save(void *opaque) +{ + ARMCPU *cpu = opaque; + + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + + return 0; +} + static int cpu_pre_load(void *opaque) { ARMCPU *cpu = opaque; @@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state = UINT32_MAX; + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + return 0; } @@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + return 0; } @@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu = { .version_id = 22, .minimum_version_id = 22, .pre_save = cpu_pre_save, + .post_save = cpu_post_save, .pre_load = cpu_pre_load, .post_load = cpu_post_load, .fields = (VMStateField[]) {