From patchwork Fri Jan 18 14:57:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 155985 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3392870jaa; Fri, 18 Jan 2019 07:36:18 -0800 (PST) X-Google-Smtp-Source: ALg8bN5zMx7Ucf/zRAfe8oaMBPdUq/2xwuhTYdPiEUiG7PW9+aSnxkFlejrqZYH9NSXgkYuDDt8w X-Received: by 2002:adf:fbc8:: with SMTP id d8mr16932084wrs.318.1547825778393; Fri, 18 Jan 2019 07:36:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547825778; cv=none; d=google.com; s=arc-20160816; b=bbopEpGfuVwiYIuq6TvfOkZF8aRCGgwWtbUrpWKwaXPKGgu1AOTDNY3yEaYQy6f4ct sjk8sR279HQcBKz4ARHBgdjdRZ028W0bF1+AbV7pxS9hYuQ70Oh5zlave4ifR/Uw4bCo WmojcY2K7MqB+xBNynAv+jeiqmVml8Lehd+aboPGdFJWe3Iub8hGjQabAfn5soxDEK+B I1pR97pEEwHc1kf7CdcY3Ts7/4oLKoep3zAo4Kz1wIjiQMrubRXjqkdKc26Z5TGTamKl 1TkpwW6OcMuF3w1O8xT6chUWG4SyVQtvBQVQB/VlKbrOSCN0PBdBM0Wzh0hlgu3FMkaV iZgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ErTaoav7h0A4GqPDm6lr9G8kaONskKumFLAjDp0b27Q=; b=VQ9WuAYtU6B64izGfnbW/zpxkQIKIEZjzriymys9/A7UeaFeDu3cjxyJPCAnQInGw3 z4tTeztdWXQzMFcukFzQagMARE3FiLJU47WU9ZH9WUR/ePuDN0o/TM8gIZv5RnGdewNr 3vRs5lsKU9HvTX0tZ/WIHEo9mbg0aDGNlVA+0fm6LWwwnF56VaE33JZ5+oUBasCH0e1j o0CC+fYKk0E2ACD37+p0a9r1W0gb95ZKSvkh4LqIuGkIJS2tFunLJ4UVdN63Y3Ew/7IS py2lX08S3Qv5Njs+w5WgsCi+3fdK7R8Ep5TWnFS1DkNZMlgxGQ6I8/BP6fU5RvtnRDVv P4GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LJGLSCax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v27si65190559wra.457.2019.01.18.07.36.18 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 18 Jan 2019 07:36:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LJGLSCax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:41584 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkWBt-0000N0-AY for patch@linaro.org; Fri, 18 Jan 2019 10:36:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43320) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVbj-00033Z-0W for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:59:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkVbh-0007c8-K2 for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:54 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:36916) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gkVbh-0007b2-BI for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:53 -0500 Received: by mail-wm1-x32f.google.com with SMTP id g67so4774415wmd.2 for ; Fri, 18 Jan 2019 06:58:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ErTaoav7h0A4GqPDm6lr9G8kaONskKumFLAjDp0b27Q=; b=LJGLSCax5DTddf3YBXGJRHXfSPtYvvUH2y6oS8dZI8dzNIkXHtMaQIWHyTuiD02Zze Wm0rFDjk1cFTos46gr9E6NoMKvOb7ZBo1sFdUOjru40TlyCBoZaLSR88TZNDqp1uQMU9 FBS4chgItvMlinEAGQ/PwwjpWQz4QbLu/wx0g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ErTaoav7h0A4GqPDm6lr9G8kaONskKumFLAjDp0b27Q=; b=YPrgjFHkmsbwuw8Hlt4r6UAf9/u6zRZqqqwgRkuu9fPI+sEbmrd0g2pPH5cQV9c9n0 hUbb1ksXy6kXFS/EIA4CTlExbi/+t2/pnVp6txxecO9p2RTndMY4UeoomyUlm/Tw76J6 r7KdhCsneFZAEAHYRfNADLFMchzhHo84gYqH2ddWQJ4OSOfHb8CKIcB2DjNdwExWXqlR IDCedNe8t/w0k7lGcLkYY4Awtlu0+a6kyfrWH5A8Pm7cUIRFQO3ac9sv+Bh20p9TXjWe W2GtTTzd3AVBfj5qg1GJoa2EYadjqypcXgsCmZ0wgPcepOBaB14bUn64BIYrRFMAfWS5 XKTQ== X-Gm-Message-State: AJcUukca8vtsgzdqMulovaPL4JiBmQkKq5mnt26Ho116AGT2PZnk4SYv 2GCHW4zSwTCMoYVJ8SD+Qt4W/QoKrfQm9A== X-Received: by 2002:a1c:6e06:: with SMTP id j6mr16522186wmc.3.1547823531715; Fri, 18 Jan 2019 06:58:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:55 +0000 Message-Id: <20190118145805.6852-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Aaron Lindsay Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++- target/arm/cpu.c | 3 ++ target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 101 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b743f7c178..964487d6863 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1002,6 +1002,12 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); +/** + * Functions to register as EL change hooks for PMU mode filtering + */ +void pmu_pre_el_change(ARMCPU *cpu, void *ignored); +void pmu_post_el_change(ARMCPU *cpu, void *ignored); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those @@ -1084,7 +1090,8 @@ void pmu_op_finish(CPUARMState *env); #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) -#define MDCR_SPME (1U << 17) +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) #define MDCR_SPD (3U << 14) #define MDCR_TDRA (1U << 11) @@ -1094,6 +1101,7 @@ void pmu_op_finish(CPUARMState *env); #define MDCR_HPME (1U << 7) #define MDCR_TPM (1U << 6) #define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 14bc24a35ae..317e10c895b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1038,6 +1038,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &= ~0xf00; + } else if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 733cfdc5a0f..2535c7dba62 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -976,10 +976,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRE 0x1 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1075,16 +1089,66 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env, return pmreg_access(env, ri, isread); } -static inline bool arm_ccnt_enabled(CPUARMState *env) +/* Returns true if the counter (pass 31 for PMCCNTR) should count events using + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { - /* This does not support checking PMCCFILTR_EL0 register */ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited, filtered; + bool secure = arm_is_secure(env); + int el = arm_current_el(env); + uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) { - return false; + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter == 31)) { + e = env->cp15.c9_pmcr & PMCRE; + } else { + e = env->cp15.mdcr_el2 & MDCR_HPME; + } + enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); + + if (!secure) { + if (el == 2 && (counter < hpmn || counter == 31)) { + prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; + } else { + prohibited = false; + } + } else { + prohibited = arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.mdcr_el3 & MDCR_SPME); } - return true; + if (prohibited && counter == 31) { + prohibited = env->cp15.c9_pmcr & PMCRDP; + } + + /* TODO Remove assert, set filter to correct PMEVTYPER */ + assert(counter == 31); + filter = env->cp15.pmccfiltr_el0; + + p = filter & PMXEVTYPER_P; + u = filter & PMXEVTYPER_U; + nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m = arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el == 0) { + filtered = secure ? u : u != nsu; + } else if (el == 1) { + filtered = secure ? p : p != nsk; + } else if (el == 2) { + filtered = !nsh; + } else { /* EL3 */ + filtered = m != p; + } + + return enabled && !prohibited && !filtered; } + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1097,7 +1161,7 @@ void pmccntr_op_start(CPUARMState *env) cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles = cycles; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -1116,7 +1180,7 @@ void pmccntr_op_start(CPUARMState *env) */ void pmccntr_op_finish(CPUARMState *env) { - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t prev_cycles = env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { @@ -1138,6 +1202,16 @@ void pmu_op_finish(CPUARMState *env) pmccntr_op_finish(env); } +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1209,6 +1283,14 @@ void pmu_op_finish(CPUARMState *env) { } +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ +} + #endif static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,