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X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 04/12] exec: Add target-specific tlb bits to MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits can be used to cache target-specific data in cputlb read from the page tables. Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642098..d4a3477d71 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this,