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[209.51.188.17]) by mx.google.com with ESMTPS id o204si499613wme.148.2019.01.28.14.43.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:43:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NdmIDKY2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcn-00072L-3n for patch@linaro.org; Mon, 28 Jan 2019 17:43:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcB-0006iZ-5Y for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRQ-0006Ic-Ns for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:46 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:46884) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFRO-0006Bz-N1 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:42 -0500 Received: by mail-ot1-x343.google.com with SMTP id w25so16140538otm.13 for ; Mon, 28 Jan 2019 14:31:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D+PDofj1o/9B5dTtIL1BwBv8O4UrkEKB0kHElaN43pE=; b=NdmIDKY2WqNM3i55GEzJfoTuSM+FZCANmO2dZQMf2ZTjKzid9qHttBI016VTpl42C+ gw8ceq5CVBehzAvgeGA9z2ogiYZJ0qJlkncHhBLRHUN8gdcGQMaWQx+dQoxwqPjjKAGf 6K64Cc577uDCMTPZjo3jTWkqARqM0IXyUM2Xg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D+PDofj1o/9B5dTtIL1BwBv8O4UrkEKB0kHElaN43pE=; b=rkOQ53dGxqyHj7JONXTsH9nzqEqEFWmICxsVSUaIrePqL5cS9juBi5PYVh6IlB5uN2 fIw0En7+RJBDm4OPJLz0yuY79Np5YAX/SAAuR/k6sHmR8wx0MkWXHaTmbiIXGxW8rkYp zaoTdp8GhWB+sRkG/NbcunM63TNMYNQQKNkCz92OqqR6WskSyRrps0WOdTJXNfLh7T/Y e+QNvBiHeKgVk+FrN0U5BaUm18AzwHFXyq8AQY4zO9MMl7xfM3TwBtQR1p2sCZ7LtwDa zhznc0bX+sx0lOaFA6bBY5c5jFjro49fB0ihQcqqRsnLNZzwoVPX7UrpnyrPH7uUe2VN XrIQ== X-Gm-Message-State: AJcUukfv9NJnn546ET8YHf11lfdQbKbNoS+0jVddljFXke6/Tloe6gQP y2fGvwX+4qa0Q1vAduVKwM+yi1vUCzY= X-Received: by 2002:a9d:6c44:: with SMTP id g4mr16550494otq.368.1548714690939; Mon, 28 Jan 2019 14:31:30 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:11 -0800 Message-Id: <20190128223118.5255-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128223118.5255-1-richard.henderson@linaro.org> References: <20190128223118.5255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v2 05/12] target/arm: Cache the GP bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Caching the bit means that we will not have to re-walk the page tables to look up the bit during translation. Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 6efe88a157..70277222da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10457,6 +10457,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10629,6 +10630,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ + guarded |= extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10674,6 +10676,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->target_tlb_bit0 = true; + } if (cacheattrs != NULL) { if (mmu_idx == ARMMMUIdx_S2NS) {