From patchwork Thu Feb 7 11:53:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157711 Delivered-To: patch@linaro.org Received: by 2002:ac9:7558:0:0:0:0:0 with SMTP id r24csp534802oct; Thu, 7 Feb 2019 03:54:37 -0800 (PST) X-Google-Smtp-Source: AHgI3IYJMkHhkissfhCeipIuOso3/yR0XP1DefolItccVcHyaIU3cb/bfXZCSAfq8WOc9rp2xHw7 X-Received: by 2002:a1c:790c:: with SMTP id l12mr6745610wme.11.1549540477700; Thu, 07 Feb 2019 03:54:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549540477; cv=none; d=google.com; s=arc-20160816; b=CKfVlxx1vI+HFqunTXvM9SIbhtv3RIlQ3NdyVN5y45pNPB2VgGqXF/ynpOsv6y/31Y UXqgFKYWXiYeb32PoQUKKF8opBrdKEMEVsT3Z9VHsfiZWzHJ9xsamgTYTCoCNIYZu6Kk MVH9KxmUwjukgfYcLmy//zuzHxqVj92bX01ZOjqH7cHW3h6gB79HLdantj3a+jG6p0Uc cHynpcoftm1NtulwKjBAmGiOn0GOqFn2poR20/wz4sZrSjI5sGhV0LdcA58xS5Emk+VD IXjWrishoYj6K8BPtsK1uGAN2kvaIqlFA/6Ry8Ubt597S2rIHHlcAnD0zStSPzl8DqzB RHqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7goFFJKY4A9PRscknR3z3GvJLJyK30VUXtPHHSCi9fc=; b=rcQbDOR69UEmSm5nJ9r4VUl8gwyWJ39WGKSPJQDa5V+9vqpY2jRBLTzry4uClpAmuw EGNtEVEAXiZ/HkcH2bg9TrAXlL6ppgfWv3aY9borVsdq9XN6ykm3HSfrODda3SEeyivc sRSqOeKo40SM6QtsXZOS1NmPM1/xzXCdxi7Gm9AWtjeq3/VCCnZrOQzFVO6bksGU6ud5 HAic++XCoVhB5L4ctC+nNrXjzIoZsFdu3xFHfgjiWgsfDzoaYzhoM/gUS3+RfpqQ1vqS bMqpt8WaB5o9mvSwb7je5cYbaHxNsYZzAPshmMalpl9xyUlStMDWC6lVAP/RIZemP+9R +U1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eArYulhQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d16si13578183wmb.173.2019.02.07.03.54.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Feb 2019 03:54:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eArYulhQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:38398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1griGK-0007Cm-Gc for patch@linaro.org; Thu, 07 Feb 2019 06:54:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1griFt-0007Ab-W9 for qemu-devel@nongnu.org; Thu, 07 Feb 2019 06:54:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1griFs-0001Nx-Ma for qemu-devel@nongnu.org; Thu, 07 Feb 2019 06:54:09 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:37884) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1griFs-0001N7-52 for qemu-devel@nongnu.org; Thu, 07 Feb 2019 06:54:08 -0500 Received: by mail-wr1-x442.google.com with SMTP id c8so4412682wrs.4 for ; Thu, 07 Feb 2019 03:54:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7goFFJKY4A9PRscknR3z3GvJLJyK30VUXtPHHSCi9fc=; b=eArYulhQneXd7Ak7WznPIfaiRjl59/ajZFeNR2mJc3G9p9jjshTk1VWMU8HIjpP53h mimdbgO3lcEBRx2whbZ1iHkBWMGyeUyjFwxbRgEDeYYXkWpxMm4SU7UT0g7N8gV8NK+p MpCJq0uADbeAIciBcDSB7vHcA3zDyUO7yaag2yuOkZslrzk/rDai2R/OCEH+qIB846bq zrwCGmQdNsnr+VWjBHvbfPBk/K1xUV7WpFqZhee25j6A7fwN5JGhm8U8kCuSrRlu0wnc L8fw/9QZlpqNpP7kdeEvF0sJVWQx+mXN1MNg57FpoX9RCtgRyTEIjilgeiHEX3yF5dDr FAjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7goFFJKY4A9PRscknR3z3GvJLJyK30VUXtPHHSCi9fc=; b=eP9YvPHyVgWNg8dJKJvqPx9jErmLdBce1GmAyNIi6iQxViAwyiRe8UkMQmq1/Yjegd fiNuUsUPMkqf6/RuGdETPJMbiN4iBgnyr3bqDke15Prs1jwkPzkGPx7MH5GlMP1RimdK GT/Y3LLsjdvgxKiNqwjh0Az8CNxf23Otph/IdvdYSJL7RGg/LmbKhRDfh1Z3A9kGKLlH OkBfA8N791/3qm3PjJRShfdn9yyyqjKQhHBM7YugWNZyIvwcaIgblqtmFFCI3ubEZslg 0qghMFQ84x2fluInJB260L43l7n56n71sMSNjW01g7vjAmE6MwjSc+EDgXKweCbQ+vBu C6gA== X-Gm-Message-State: AHQUAub0OQny1Ct3Y1i8PmsLBTUdd6zKi7wyLJdCkXv9IRMiVY85qaQD SYDmb0xPl9fXubvzXDia6ldYM1/8mTn2tw== X-Received: by 2002:adf:f181:: with SMTP id h1mr9958989wro.95.1549540446638; Thu, 07 Feb 2019 03:54:06 -0800 (PST) Received: from cloudburst.twiddle.net ([37.205.61.206]) by smtp.gmail.com with ESMTPSA id w16sm34030016wrp.1.2019.02.07.03.54.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 03:54:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Feb 2019 11:53:44 +0000 Message-Id: <20190207115400.647-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190207115400.647-1-richard.henderson@linaro.org> References: <20190207115400.647-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 03/19] target/hppa: Convert move to/from system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de, svens@stackframe.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 61 +++++++++++++++++----------------------- target/hppa/insns.decode | 15 ++++++++++ 2 files changed, 41 insertions(+), 35 deletions(-) -- 2.17.2 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f50ec7b9c2..72cb7b477e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -838,7 +838,7 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } -static unsigned assemble_sr3(uint32_t insn) +static inline unsigned assemble_sr3(uint32_t insn) { unsigned s2 = extract32(insn, 13, 1); unsigned s0 = extract32(insn, 14, 2); @@ -2005,9 +2005,9 @@ static bool trans_sync(DisasContext *ctx, uint32_t insn, const DisasInsn *di) return true; } -static bool trans_mfia(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { - unsigned rt = extract32(insn, 0, 5); + unsigned rt = a->t; TCGv_reg tmp = dest_gpr(ctx, rt); tcg_gen_movi_reg(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); @@ -2016,10 +2016,10 @@ static bool trans_mfia(DisasContext *ctx, uint32_t insn, const DisasInsn *di) return true; } -static bool trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) { - unsigned rt = extract32(insn, 0, 5); - unsigned rs = assemble_sr3(insn); + unsigned rt = a->t; + unsigned rs = a->sp; TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_reg t1 = tcg_temp_new(); @@ -2035,16 +2035,16 @@ static bool trans_mfsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) return true; } -static bool trans_mfctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) { - unsigned rt = extract32(insn, 0, 5); - unsigned ctl = extract32(insn, 21, 5); + unsigned rt = a->t; + unsigned ctl = a->r; TCGv_reg tmp; switch (ctl) { case CR_SAR: #ifdef TARGET_HPPA64 - if (extract32(insn, 14, 1) == 0) { + if (a->e == 0) { /* MFSAR without ,W masks low 5 bits. */ tmp = dest_gpr(ctx, rt); tcg_gen_andi_reg(tmp, cpu_sar, 31); @@ -2086,10 +2086,10 @@ static bool trans_mfctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) return true; } -static bool trans_mtsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) { - unsigned rr = extract32(insn, 16, 5); - unsigned rs = assemble_sr3(insn); + unsigned rr = a->r; + unsigned rs = a->sp; TCGv_i64 t64; if (rs >= 5) { @@ -2112,11 +2112,10 @@ static bool trans_mtsp(DisasContext *ctx, uint32_t insn, const DisasInsn *di) return nullify_end(ctx); } -static bool trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) { - unsigned rin = extract32(insn, 16, 5); - unsigned ctl = extract32(insn, 21, 5); - TCGv_reg reg = load_gpr(ctx, rin); + unsigned ctl = a->t; + TCGv_reg reg = load_gpr(ctx, a->r); TCGv_reg tmp; if (ctl == CR_SAR) { @@ -2132,9 +2131,7 @@ static bool trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) /* All other control registers are privileged or read-only. */ CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); -#ifdef CONFIG_USER_ONLY - g_assert_not_reached(); -#else +#ifndef CONFIG_USER_ONLY nullify_over(ctx); switch (ctl) { case CR_IT: @@ -2168,12 +2165,11 @@ static bool trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) #endif } -static bool trans_mtsarcm(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) { - unsigned rin = extract32(insn, 16, 5); TCGv_reg tmp = tcg_temp_new(); - tcg_gen_not_reg(tmp, load_gpr(ctx, rin)); + tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); tcg_temp_free(tmp); @@ -2261,24 +2257,26 @@ static bool trans_ssm(DisasContext *ctx, uint32_t insn, const DisasInsn *di) ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; return nullify_end(ctx); } +#endif /* !CONFIG_USER_ONLY */ -static bool trans_mtsm(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) { - unsigned rr = extract32(insn, 16, 5); - TCGv_reg tmp, reg; - CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + TCGv_reg tmp, reg; nullify_over(ctx); - reg = load_gpr(ctx, rr); + reg = load_gpr(ctx, a->r); tmp = get_temp(ctx); gen_helper_swap_system_mask(tmp, cpu_env, reg); /* Exit the TB to recognize new interrupts. */ ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; return nullify_end(ctx); +#endif } +#ifndef CONFIG_USER_ONLY static bool trans_rfi(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { unsigned comp = extract32(insn, 5, 4); @@ -2317,19 +2315,12 @@ static bool gen_hlt(DisasContext *ctx, int reset) #endif /* !CONFIG_USER_ONLY */ static const DisasInsn table_system[] = { - { 0x00001820u, 0xffe01fffu, trans_mtsp }, - { 0x00001840u, 0xfc00ffffu, trans_mtctl }, - { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, - { 0x000014a0u, 0xffffffe0u, trans_mfia }, - { 0x000004a0u, 0xffff1fe0u, trans_mfsp }, - { 0x000008a0u, 0xfc1fbfe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, /* sync */ { 0x00100400u, 0xffffffffu, trans_sync }, /* syncdma */ { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, #ifndef CONFIG_USER_ONLY { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, - { 0x00001860u, 0xffe0ffffu, trans_mtsm }, { 0x00000c00u, 0xfffffe1fu, trans_rfi }, #endif }; diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 2822fbc58b..047a9d01ec 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -17,8 +17,23 @@ # License along with this library; if not, see . # +#### +# Field definitions +#### + +%assemble_sr3 13:1 14:2 + #### # System #### break 000000 ----- ----- --- 00000000 ----- + +mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 +mtctl 000000 t:5 r:5 --- 11000010 00000 +mtsarcm 000000 01011 r:5 --- 11000110 00000 +mtsm 000000 00000 r:5 000 11000011 00000 + +mfia 000000 ----- 00000 --- 10100101 t:5 +mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 +mfctl 000000 r:5 00000- e:1 -01000101 t:5