From patchwork Mon Feb 11 01:08:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157953 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2063510jaa; Sun, 10 Feb 2019 17:22:23 -0800 (PST) X-Google-Smtp-Source: AHgI3IZIlLoAj2mz4pmPDiW4wOlWApnJX9En2Enq+LzkTiPcDhpOTFa6BaQKD0FxCwLdRBZqzzQB X-Received: by 2002:adf:ec47:: with SMTP id w7mr23242867wrn.8.1549848143546; Sun, 10 Feb 2019 17:22:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848143; cv=none; d=google.com; s=arc-20160816; b=mnf7yLCnKoOwid2RhPsmy/aw6GDJwTT0BWOsh/nsFTJJyw03aSNVJSeIRqnyP7vEOA VcWx/9OO13wNI7tHQWePKg3/m0x7wdpmfdxqSnNR0HQwGy3GWSPBSoMBpbcRsl9+TwaI 6hPsuGc9mNLDjPjZGjZJ/SHNf/Hj6V0eomrBhEPm6EyMR0913WgloM1iCZYKihQAl25f WHbNov1UVlLBGv5pfQNrCxZvPgaq2q+U3/w738ywBwOEe5whzXPPCLXmhBAAnrA9oNjz B8Ha2hvw1aLFtfH9LDXBZmQeQ3onGRUm9VSR1zOeMAQnGoxFTjXJp5uoLpDM4XDmyb7u EpTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=zcAWarDqxyWQsApIH1+QUdK4n2qbjboVNC3ZYTwk7ey7eTZkFwW/Dleb7hEztEV2Rs b4Zv2LHbn5jXmMU2x2jjBuw2V6zwHAwFtlLUNH2QlUHZo0oscW2ih3VbSvR/ngWidDdN KrrGhnmjtVPQiLIwWnp3BOjvWUgmYu/LXVyjbzK/pjJ87wSbQ7iNBSgEYvFh2Qe0Gy2j 9WT1FryZg30dMiK+0ntFdf6n+vMUrntZOZnk4pqUHsdqvSfXVicWkQyG6KG3HNuA+xU6 gmJv3ZK7ee7XyW2u0rzWUWdT0VXdcpFchwSGnj6iUyD81zhpdJUpx6rlbkCpHRYPFTR3 09KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sJ6MFe1O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d9si6147819wrs.133.2019.02.10.17.22.23 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 10 Feb 2019 17:22:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sJ6MFe1O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:42266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Ig-0006n9-Ba for patch@linaro.org; Sun, 10 Feb 2019 20:22:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05r-0005sa-M9 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05p-0008Vv-TQ for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:07 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:36069) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05o-00085p-54 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:05 -0500 Received: by mail-pl1-x635.google.com with SMTP id g9so4514744plo.3 for ; Sun, 10 Feb 2019 17:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=sJ6MFe1O9QLLEm0oNmM3TWjy7Y4iPUj26h91DwSCp4z74dlfzii4jjdnDkwUlIvKdJ puuyz0A3lYE/ShWtJ2uek0f782rfPe67kvRvfQJzbS2CEusicN86rhVysDyI0p39pdJE wovlj8XBud1Apk/+mEyV1jsaIcPINA2EyPo4D7cTTrk+q/Av8Fyj02/nhE7M7V4+30Km H87wCqrYg68JsrvGzdksCs/57rsAwPBnI/aHF/L18i6LPqhldm9ioY926+gUtrIdngpn KNfFydJXdSHXpUxwUgEMB+lE35VL98Pz7NtTq5ajfT33JopIII+SDm2pHtSGXnOJoUez +LCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=S5QTCECFOTTOWuBZ6jCDCOWz54HdRtRqVjL/0c1VTuJizHggAM6/znpKbSZ/ZIYQHw 9VmsxzrghqmawERzP61Sc+nC0TtaknrURsrAtMhkQu1YOfh3aun/7zN1ShOJJx8zHQSj O/7bSH4MDZhGcsmJa3h0vv5req4y292op8sWqPeLBp6utLQtlBZNfT3wsGsrudkbzyX0 /4Qh60tnaK+QMc+ka7KtO4tUyV/5/OLZX/VIZYo6FKlANrImGh0j7ZCFPXzh0T4clKH3 92eDdm9wOeGQmE6aus4lb/CnEwF6727Cios6ZFQU9iV5WAKUjsAwtsgUqe+gtgO7WpiU 5dkQ== X-Gm-Message-State: AHQUAuZbEFq0EVzz2rfkcZHGdvQ+/uNtgw+xiRa3JnOzoF1vrWUgByRt IEDKHp7k26UxfsVPy88C9BIU75hIWvo= X-Received: by 2002:a17:902:298a:: with SMTP id h10mr35277076plb.312.1549847322224; Sun, 10 Feb 2019 17:08:42 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:11 -0800 Message-Id: <20190211010829.29869-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH v2 08/26] target/arm: Fill in helper_mte_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. --- target/arm/mte_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index f1174d6f9f..d086925a91 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,6 +25,8 @@ #include "exec/helper-proto.h" +#if 0 +/* Don't break bisect. This will gain another user before we're done. */ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) { /* @@ -49,9 +51,97 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) return ptr; } } +#endif + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { - /* Only unchecked implemented so far. */ - return strip_tbi(env, ptr); + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, true); + int el = arm_current_el(env); + int ptr_tag, mem_tag; + uintptr_t ra = GETPC(); + + /* + * If TBI is disabled, then the access is unchecked. + * While we filtered out TBI0==0 && TBI1==0 in cpu_get_tb_cpu_state, + * we did not save separate bits for TBI0 != TBI1. + */ + if (!param.tbi) { + /* Do not ignore the top byte. */ + return ptr; + } + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(ptr); + if (param.tcma && ptr_tag == 0) { + goto pass; + } + + /* + * If an access is made to an address that does not provide tag storage, + * the result is implementation defined (R0006). We choose to treat the + * access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, ptr, ra); + if (mem_tag < 0) { + goto pass; + } + + /* If the tags do not match, the tag check operation fails. */ + if (ptr_tag != mem_tag) { + int tcf; + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf = extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf = extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf == 1) { + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(ENV_GET_CPU(env), ra, true); + env->exception.vaddress = ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + } else if (tcf == 2) { + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[el] |= 1 << param.select; + } + } + + pass: + /* + * Unchecked, tag check pass, or tag check fail does not trap. + * Ignore the top byte. + */ + if (el >= 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return extract64(ptr, 0, 56); + } else { + return sextract64(ptr, 0, 56); + } }