From patchwork Thu Feb 14 12:51:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 158379 Delivered-To: patches@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1325969jaa; Thu, 14 Feb 2019 04:51:26 -0800 (PST) X-Received: by 2002:a5d:5681:: with SMTP id f1mr2446154wrv.95.1550148686534; Thu, 14 Feb 2019 04:51:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550148686; cv=none; d=google.com; s=arc-20160816; b=vOp0BsqcY+8I35xPM4mdvGsvg/9iJWLXHj52MHBjiod2k3N6rpYIP8XXvnh95A1ZqT IdZmcQD+pmajuaRr1PQSRzdmN3OhZtduh0bKQrhFkgzhED0LpNBDh0gEU8ghLJxUEGjE kMvgz9yIHaWUzSmRU91GZpSp6sTK2y+KveVGMOKXPyx8IgEYCgIbgkhAsyBoSE9HYyX6 78+a22nZCB5UmnnTWqKU/H6yDHdefstZainCfmpUDERKZUzmljvaYXH7r/dKuT0AYj1t RR86StaAKonlaQDA0l2iojUDp0EX2vjdv7Rp3pu0R9yPAqJldb7/xxpO2wf9iwd3oQkk QzLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7g9zWEgPnQ1/3e/7FE39QU99XF4zWTWG/yRPa1dvYJ4=; b=mcs521CVHASaSw4TN+IASPviGmC3CV3Dnh1bl8PnMGlhnfsGxrm1UWgklr6vpPsjjR r3YvseWtcV4oWHjggtNlRJqG/VUfOTEIAiW82Ly04hoa6W2y5U0CbWv71VUCQkv/F/PZ 2knHSYJhRyF+CcJdYA5PM+nUxT+94XaWBIsn97teCglu0TqLxNmjYLoT89vB+oTrhZcM tZS5Y6HzO13XZVHYuD0XHynXEXu+PFaKIx5/Q/NaxXXSbmdxOz4kXl8sc6AhJ0CdvUVD YnODO8rxMyR0k2VsVTqTQWVPjVnsNrK0y/QPIl2Yzw25+bH78S82mjY2lqfUm+mqokf3 ZprA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L9Ajd4o6; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id l7sor1609292wrr.32.2019.02.14.04.51.26 for (Google Transport Security); Thu, 14 Feb 2019 04:51:26 -0800 (PST) Received-SPF: pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L9Ajd4o6; spf=pass (google.com: domain of peter.maydell@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.maydell@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7g9zWEgPnQ1/3e/7FE39QU99XF4zWTWG/yRPa1dvYJ4=; b=L9Ajd4o6Pgb6p4DcApMyojBNs9E6icveqCja/w7bkw12ndkmgLBvoUw4QhfXU1wvOr LQan0eZiJUA5nXl+sFcUbHdHmEaXV2uTteAytSPuM0aHhd+3Z12bK0gtodDpli/kwYEC L2S6OHfQsllwdeLRH0kuXwv0x2ARSJxViyFN/cRlsspPzEat+N4j5dthn4dgYbj5SUET YdnP8ON+n23dxzaCEP4S+jBkavrftozrRnv+DLHGmq0pJ68nqOh+kOtjLOYScepBHYUv Ez7qfNwfEW1wlKz03WmJPP/NSJaBxhpxnHnsXzIrsfVaI7HnhSv+boTtrcn99f6rKLlq TcFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7g9zWEgPnQ1/3e/7FE39QU99XF4zWTWG/yRPa1dvYJ4=; b=II2YsFqHDko8G6NvUIBN6gvNLvlxK+imnHw7oFivTCfZ4CBcml1eC0TdcCaFi0C7G2 WZfLnVs2OnuJsYjDp0rcywL5KdyGnEi1NjQbi1+7ttFV4asdsGEjDTeWoGtgcQ694Amj TnIXhBmKuqOGLpCppI+/dCyLYBh88kuuL/JWyuR7lITm/eWJHxhH1rHHuMGlLD2MHF1w THSqQvbXPAH5/QupabP4TpTsCEg7gLGzC5KIhp5i5PkEAd3KcAKW9NqtzaTLv3MW1H4J 7wZ2UW6vhq6i3Khk51NbmgjKNY9NZU+ownASL0WcgDrn55td3UzUamy6Fdes1W5Ri1LW KApw== X-Gm-Message-State: AHQUAuZ7vW9cC4CX3rLdGXPNEii1C7+FbvWd3Yyoqm2bqT++vRmamQgB iiKSbPv8juuVNB+uIZLtvTwYMusD X-Google-Smtp-Source: AHgI3IbZ6vjOb50UZ5Am2kF8GzOc9x30M/qDdswoDLgh12yziXtxBknfDecvSx5K5B3gSzow5XaUww== X-Received: by 2002:a05:6000:1287:: with SMTP id f7mr2882462wrx.203.1550148686149; Thu, 14 Feb 2019 04:51:26 -0800 (PST) Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 14/14] hw/arm/musca: Wire up PL011 UARTs Date: Thu, 14 Feb 2019 12:51:07 +0000 Message-Id: <20190214125107.22178-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Wire up the two PL011 UARTs in the Musca board. Signed-off-by: Peter Maydell --- hw/arm/musca.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/musca.c b/hw/arm/musca.c index ec8dfee1964..e9701533d20 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -23,9 +23,11 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" #include "hw/arm/arm.h" #include "hw/arm/armsse.h" #include "hw/boards.h" +#include "hw/char/pl011.h" #include "hw/core/split-irq.h" #include "hw/misc/tz-mpc.h" #include "hw/misc/tz-ppc.h" @@ -69,7 +71,7 @@ typedef struct { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState pwm[3]; UnimplementedDeviceState i2s; - UnimplementedDeviceState uart[2]; + PL011State uart[2]; UnimplementedDeviceState i2c[2]; UnimplementedDeviceState spi; UnimplementedDeviceState scc; @@ -285,6 +287,28 @@ static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); } +static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque, + const char *name, hwaddr size) +{ + PL011State *uart = opaque; + int i = uart - &mms->uart[0]; + int irqbase = 7 + i * 6; + SysBusDevice *s; + + sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), + TYPE_PL011); + qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); + s = SYS_BUS_DEVICE(uart); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */ + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */ + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */ + sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */ + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */ + sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */ + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); +} + static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque, const char *name, hwaddr size) { @@ -300,8 +324,8 @@ static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque, MemoryRegion *container = &mms->container; const PPCPortInfo devices[] = { - { "uart0", make_unimp_dev, &mms->uart[0], 0x1000, 0x1000 }, - { "uart1", make_unimp_dev, &mms->uart[1], 0x2000, 0x1000 }, + { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 }, + { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 }, { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 }, { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 }, { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, @@ -460,8 +484,8 @@ static void musca_init(MachineState *machine) { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 }, { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 }, { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 }, - { "uart0", make_unimp_dev, &mms->uart[0], 0x40105000, 0x1000 }, - { "uart1", make_unimp_dev, &mms->uart[1], 0x40106000, 0x1000 }, + { "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 }, + { "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 }, { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 }, { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 }, { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 },