From patchwork Thu Feb 14 19:05:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 158439 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1761299jaa; Thu, 14 Feb 2019 11:21:54 -0800 (PST) X-Google-Smtp-Source: AHgI3IYl9L6C7ulwaRk1RgFvqR+sepU6Qsfpwj+2dRuZIn8XiNsKfO24STVBi9dbE/4GTTNvJQbE X-Received: by 2002:a0d:c182:: with SMTP id c124mr4692304ywd.190.1550172114128; Thu, 14 Feb 2019 11:21:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550172114; cv=none; d=google.com; s=arc-20160816; b=oC2mwtB56nu0d3cY0fFXr9ztUY9a4wzHtYo1sCUEluAdn1S8ciYlghCmftX5fJ0Fa3 f+08T+5jtypjW9AeJNdb53SdP2iTO7gp8u4ZwyAtXtxVuPXd5uNUqcZ4naYkQXYIUxpv LmfO+hr8Z2XPInIBmrvrlcZ9TOTUsS/TlXptHNeiEcDKv39oIFg+hSB3AOLjHW4X9LG7 vvk0sI5S/0E4ZyanDVYKV4CDi2Y48SgFuG3B7IU4sSbdXR/az6TtPw88+JhH4CcwrWYl Cs0Dim1RYDTgUWE57yyHNw9TYlpEMaqf3y3KM8O0tZFT/CC6N23h1mY7go6CuyxXAaKw 62Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IAycNoOEPKuwngOeVGLHyewoQkDCL7EmRZgOMvphgKY=; b=Q9Pp97hLAXOmd0CavogOLRsjUfb39JRLIPZbzr6zdj2SBxsImNGQV/1roQUEfZx5SW alAEQHlKxGRLlWTnYQR/j0udWb1cp3bmzf6yz/ybICpDReFrmAWac97s1cw0lHYc2T1b K4lVw7sOwG2KztrVtiRnW9TbzOPtmLHufj14V4XuEllN9Y5WYvSfDphvXfj9/HIywEvo 0QSYKFQmBspgz5WqB2hjE3ttmxbMT3sn8zy1HOn/JkbzwRCrbQk11acOvs1PU8FFOhNT KJL8osDfEQHvO0v6JOxfN1VghNQpCSgJ1yHVHOKhQe25SiGhiPpd8rt8eXxkfzExrkrV KSMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Yf4t6ZM/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t185si1962145ybf.403.2019.02.14.11.21.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Feb 2019 11:21:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Yf4t6ZM/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:53733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guMa1-00033G-KT for patch@linaro.org; Thu, 14 Feb 2019 14:21:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guMLL-00084I-Ie for qemu-devel@nongnu.org; Thu, 14 Feb 2019 14:06:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guMLK-0004uj-C4 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 14:06:43 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:52843) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guMLJ-0004pZ-V1 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 14:06:42 -0500 Received: by mail-wm1-x331.google.com with SMTP id m1so7512930wml.2 for ; Thu, 14 Feb 2019 11:06:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IAycNoOEPKuwngOeVGLHyewoQkDCL7EmRZgOMvphgKY=; b=Yf4t6ZM/a64fwhF8SkJCye9SNF8kbemgN1K+OH1jSU0PbXtIDY4zEmU5XykfPtDO0R ALipcsk5W2u7n23U2tA5dYinRz8o0zN463zs+xukeSEu1CY02OjcTyqlOByZKcursUMG hAA8ZSMQ9WhwXS+aAMcTvmtbE+XUEduTVxtsmphlwSrmY/HEREYb3QZiEtJF2Iu6AJh6 7LYp+5aXT1If+K3yVl+/vid0+avJkqgK1QtWe9Rt6qJB4basDM19QY+Mr3F3dToz5Tj4 PhMSgUEubU2oFjWtCRfC059S0Hw4p+veEmcRCPdWrXzqAJu5fBDxps1Csy/pJgyzzIKf Wcog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IAycNoOEPKuwngOeVGLHyewoQkDCL7EmRZgOMvphgKY=; b=JXISTheOoHi8ZprEM54wwn0NnzLooPYxOr0D2zG2S3UgAcpRqlR/KY9Fv+UVtB6McL sQpSQ5/h36iqeMo8zS8Z6AnqNyzdTZhofQdkmaz3QG3yj8w0/rPcJfWtYb30xP6XCUZE kXNwL2VbHscZdy6M/ARL7KvhbXyE15VCVcGHKQOrQLEs+zPmTP2SNv3h+iTnzmpmy242 0Bh5F85ISoQyQOXr1sdRY81WjCcGqB0X95iLRJVXXMn0tNdnIT9vike1lHgcUnZ4BCjS BfMtrVlTfcOVLDg4a5B12pgP0+78CWzQSKGactGM/zq70gpRrWtCaJU1cT/BsoK3vTqH wExA== X-Gm-Message-State: AHQUAua7goz915XCpJ1afFTdMD3LpOmOANgR3wUr9eRevv5CO+PW69PW /lauE6O5lRPDevt2ZNJx7Q/79q6kAD0Egg== X-Received: by 2002:a1c:a5cc:: with SMTP id o195mr1996040wme.67.1550171193411; Thu, 14 Feb 2019 11:06:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n184sm7798471wmf.5.2019.02.14.11.06.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 11:06:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 19:05:59 +0000 Message-Id: <20190214190603.25030-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214190603.25030-1-peter.maydell@linaro.org> References: <20190214190603.25030-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 Subject: [Qemu-devel] [PULL 23/27] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson Message-id: 20190209033847.9014-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 28e45f0f0ba..d4b7eca30a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12707,7 +12707,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) int i; uint32_t fpscr; - fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) + fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); @@ -12749,7 +12749,7 @@ static inline int vfp_exceptbits_to_host(int target_bits) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { int i; - uint32_t changed; + uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { @@ -12758,12 +12758,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) /* * We don't implement trapped exception handling, so the - * trap enable bits are all RAZ/WI (not RES0!) + * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) + * + * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC + * (which are stored in fp_status), and the other RES0 bits + * in between, then we clear all of the low 16 bits. */ - val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE); - - changed = env->vfp.xregs[ARM_VFP_FPSCR]; - env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000; env->vfp.vec_len = (val >> 16) & 7; env->vfp.vec_stride = (val >> 20) & 3;