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[209.51.188.17]) by mx.google.com with ESMTPS id s66si8269665ywc.5.2019.02.18.07.04.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 18 Feb 2019 07:04:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=GyMGAJOO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:60090 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gvkTF-0007e9-TK for patch@linaro.org; Mon, 18 Feb 2019 10:04:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gvjyY-00078K-9K for qemu-devel@nongnu.org; Mon, 18 Feb 2019 09:32:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gvjyW-0003Yy-IR for qemu-devel@nongnu.org; Mon, 18 Feb 2019 09:32:54 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:35565) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gvjyV-0003HO-Ud; Mon, 18 Feb 2019 09:32:52 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4435s36xsCz9sNp; Tue, 19 Feb 2019 01:31:18 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1550500279; bh=SbFTW5ArUtzfEMNfc+DBJyifayJX+tu5Lp1EoIkfjWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GyMGAJOO8145/FO+/TMohslqmPc1pJeCtLPkhXCxAjZUUNvLNtnhKpmz+CMJUAvZm Dt0Pa+R/60ekrzBlMubxo+ws9hRVD7MLfLM1/5uU1mu488vnl4oFKRT79BXUp1UeHS taXECYcQonmS+2khgMUeZaIrl4xZCZGmn0rUVEsQ= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 19 Feb 2019 01:30:47 +1100 Message-Id: <20190218143049.17142-42-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190218143049.17142-1-david@gibson.dropbear.id.au> References: <20190218143049.17142-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 41/43] target/ppc: Split out VSCR_SAT to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Change the representation of VSCR_SAT such that it is easy to set from vector code. Signed-off-by: Richard Henderson Acked-by: David Gibson Message-Id: <20190215100058.20015-16-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 +++- target/ppc/int_helper.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1c883fa836..325ebbeb98 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1052,10 +1052,12 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Vector status and control register */ + /* Vector status and control register, minus VSCR_SAT. */ uint32_t vscr; /* VSX registers (including FP and AVR) */ ppc_vsr_t vsr[64] QEMU_ALIGNED(16); + /* Non-zero if and only if VSCR_SAT should be set. */ + ppc_vsr_t vscr_sat QEMU_ALIGNED(16); /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 1d8a4b530b..6ad596a08b 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -459,18 +459,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh) void helper_mtvscr(CPUPPCState *env, uint32_t vscr) { - env->vscr = vscr; + env->vscr = vscr & ~(1u << VSCR_SAT); + /* Which bit we set is completely arbitrary, but clear the rest. */ + env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); + env->vscr_sat.u64[1] = 0; set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } uint32_t helper_mfvscr(CPUPPCState *env) { - return env->vscr; + uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0; + return env->vscr | (sat << VSCR_SAT); } static inline void set_vscr_sat(CPUPPCState *env) { - env->vscr |= 1 << VSCR_SAT; + /* The choice of non-zero value is arbitrary. */ + env->vscr_sat.u32[0] = 1; } void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)