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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:31 -0800 Message-Id: <20190307170440.3113-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 13/22] target/arm: Implement the LDGM and STGM instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Require pre-cleaned addresses. --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 42 +++++++++++++---- 3 files changed, 132 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 91e6a6ea94..5bcdfcf81b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -114,3 +114,6 @@ DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e8873f1e75..afa4c26535 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -377,3 +377,99 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) { do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); } + +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, false, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are loading 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + return ldq_le_p(mem); +} + +static uint64_t do_stgm(CPUARMState *env, uint64_t ptr, + uint64_t val, uintptr_t ra) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* + * No action if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return ptr; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are storing 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + stq_le_p(mem, val); + + return ptr; +} + +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + do_stgm(env, ptr, val, GETPC()); +} + +void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int i, mmu_idx, size = 4 << GMID_EL1_BS; + uintptr_t ra = GETPC(); + void *mem; + + ptr = do_stgm(env, ptr, val, ra); + + /* + * We will have just probed this virtual address in do_stgm. + * If the tlb_vaddr_to_host fails, then the memory is not ram, + * or is monitored in some other way. Fall back to stores. + */ + mmu_idx = cpu_mmu_index(env, false); + mem = tlb_vaddr_to_host(env, ptr, MMU_DATA_STORE, mmu_idx); + if (mem) { + memset(mem, 0, size); + } else { + for (i = 0; i < size; i += 8) { + cpu_stq_data_ra(env, ptr + i, 0, ra); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7175897e4..e02d85f317 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3722,7 +3722,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 = extract32(insn, 10, 3); int op1 = extract32(insn, 22, 2); - bool is_load = false, is_pair = false, is_zero = false; + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; int index = 0; TCGv_i64 dirty_addr, clean_addr, tcg_rt; @@ -3732,13 +3732,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) } switch (op1) { - case 0: /* STG */ + case 0: if (op2 != 0) { /* STG */ index = op2 - 2; - break; + } else { + /* STZGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_zero = true; } - goto do_unallocated; + break; case 1: if (op2 != 0) { /* STZG */ @@ -3754,17 +3759,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) /* ST2G */ is_pair = true; index = op2 - 2; - break; + } else { + /* STGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = true; } - goto do_unallocated; + break; case 3: if (op2 != 0) { /* STZ2G */ is_pair = is_zero = true; index = op2 - 2; - break; + } else { + /* LDGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_load = true; } - goto do_unallocated; + break; default: do_unallocated: @@ -3781,7 +3796,16 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) clean_addr = clean_data_tbi(s, dirty_addr, false); tcg_rt = cpu_reg(s, rt); - if (is_load) { + if (is_mult) { + if (is_load) { + gen_helper_ldgm(tcg_rt, cpu_env, clean_addr); + } else if (is_zero) { + gen_helper_stzgm(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stgm(cpu_env, clean_addr, tcg_rt); + } + return; + } else if (is_load) { gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (is_pair) {