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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:39 -0800 Message-Id: <20190307170440.3113-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v4 21/22] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6d0f82eb99..6657f57ca6 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,8 +28,64 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + uintptr_t index; + int mmu_idx; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + hwaddr physaddr, tag_physaddr; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); + } + + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + if (!cpu_get_address_space(cs, ARMASIdx_TAG)) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + + /* Find the memory backing the tag address in tag address space. */ + mmu_idx = arm_to_core_mmu_idx(ARMMMUIdx_TagNS); + te = tlb_entry(env, mmu_idx, tag_physaddr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, tag_physaddr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, tag_physaddr, 1, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + te = tlb_entry(env, mmu_idx, tag_physaddr); + } + + return (void *)(tag_physaddr + te->addend); +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra)