From patchwork Tue Apr 16 12:57:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 162327 Delivered-To: patch@linaro.org Received: by 2002:ac9:2a84:0:0:0:0:0 with SMTP id p4csp4022844oca; Tue, 16 Apr 2019 06:09:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqzKdOzq0YQ588GakpMpqanNmKZ7sPxAaM7EWe4q4MqGGIgCQzE0MEtf8sRPImKaUhTK5ce4 X-Received: by 2002:adf:dc4a:: with SMTP id m10mr51098174wrj.0.1555420186478; Tue, 16 Apr 2019 06:09:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555420186; cv=none; d=google.com; s=arc-20160816; b=JsttKIIYB6CRXTx6jFiK0NZt2376fSu5AdKkBu04osbPVD9nU44unTuTcnxxP6NgWP akpVjB77ENMbEQcHcwlXPQFiO/p2B9wYr7U0/8kiN8Yxsb+n9sC1JuaezdNPN6nD5Fln xSqmx/XgRKT/Hjezp8bII9ZzSD6dWmkIE4hB2+lVII8Owjs2ztOskLCbu+WS50igOjqJ dh+rOq3Cz2UobqjmnRUXCqXbHi5ObJCYQLG692fIyqHp0zl38o6AiQm21KsZCsmAPKtu P+oNTtOLCp2b9q36r0/xzn+9vhM7Y+ztY30A6YjjKTCpw99LhdqYGHs1A0uRm2og4rtu mu+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aQ6wGPLx3WRt+frxzRIZZzBI6Q8JRULb0Aj0I2glCjQ=; b=PeuO4XXOxl90uiDpABSdXD7UGHZvph7jQlLMPuiV1ErPk8Tkca+3wWk20h9IrERwF6 RLqZDICfGRct5sbSiF35Q16AaGuP9kmecRgWya+CeZ6WmNQq9UE1BW9T9YvGuUOlT831 l2A40deIp34QKpDKWUnDqRhxHBEbglO6o3ut3TpIjGkhJXiJJRx63cSY8iJO48B6vFej USAdN2cUlGiJBc0BJSQPWPwc6xyuCDVB8XC1AR3U33K+iIklgTr1AMk5VUSInRrr138U DXHHagvlLr048+b9yzyPaji37g7yCEKMiWLJUQN+BWD2t5NP20DW/buZidrsObauqWrA wmUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SFSebnJU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n17si12794916wmh.112.2019.04.16.06.09.46 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Apr 2019 06:09:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SFSebnJU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:36433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNqL-00064T-7F for patch@linaro.org; Tue, 16 Apr 2019 09:09:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGNf9-0004dL-52 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGNf7-0001CQ-9B for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:11 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41749) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hGNf6-00013V-R3 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 08:58:09 -0400 Received: by mail-wr1-x443.google.com with SMTP id r4so26905548wrq.8 for ; Tue, 16 Apr 2019 05:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aQ6wGPLx3WRt+frxzRIZZzBI6Q8JRULb0Aj0I2glCjQ=; b=SFSebnJUN/iho+FW5EGiA9RNR+U2xEAyxH+PqywlPZ6RuQZA+uj8OamWP0T0+JSy/x 1K8xn131gaWUzhse5YsoPxHFyoz94XWqQCIkLOdryUMd/LnJ0Qx+Gg5J1zmlp0pp/dlB 48+qqlDaotJGJbGYllYWY+BrLsBSGIAme/wRSF37wQXVPmA9seipxy95ZCjmoXKY+JOH 5G/FHS+wqj/hbgdseEXE0+MnakC8Hw7PQyWYrIhd0oDGOjiGblljgHKbfNy2k4hvP/FX 1nmCQ3D95FhGwjE7+jAfLzIQNeD9airzZHOvEiBaQCZjck6eJtwa5EOvax4FFreuOVcT nQ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aQ6wGPLx3WRt+frxzRIZZzBI6Q8JRULb0Aj0I2glCjQ=; b=LU8VYB2j+CPVVdL3zh0mbL96QdLcpRtwhBGkjHSeHD+MdJhS4AYKu6x4uKDW2J/B90 1k68St3so5wCUaOspQ6BAiDOXOGnRw2InEFbgekaUcxtyhHTm1aoqIVFU+6MWag9+5Pu gskhpDof4EkZxnUjs5Yt11Z254rlmAbBdT/VDKtjvSDxwQUodcS1qXUW0HeC056KKKRp E3Wfegh7M7NZa9Qgzva6RaRjOxHB00GFem6+K+WYoiXvv1AyGImlldecb9YfAi9BUp5H 99KImIZqWdp7g7LQofqG7UNVnX0OZv3sQWLA1M5K2mdIuflDZILu5Bs3c6vNn0z2ANAD un6w== X-Gm-Message-State: APjAAAVQ7qCm4e5MmqlUYPeq7oG8FR/i3X54tuTjmB+U6o4KN/LJwRZP xtrdYZWFPP54F3yIcYiF6Zxz9A== X-Received: by 2002:adf:efc1:: with SMTP id i1mr51644628wrp.199.1555419476820; Tue, 16 Apr 2019 05:57:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.57.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:57:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:23 +0100 Message-Id: <20190416125744.27770-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 05/26] target/arm: Honour M-profile FP enable bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like AArch64, M-profile floating point has no FPEXC enable bit to gate floating point; so always set the VFPEN TB flag. M-profile also has CPACR and NSACR similar to A-profile; they behave slightly differently: * the CPACR is banked between Secure and Non-Secure * if the NSACR forces a trap then this is taken to the Secure state, not the Non-Secure state Honour the CPACR and NSACR settings. The NSACR handling requires us to borrow the exception.target_el field (usually meaningless for M profile) to distinguish the NOCP UsageFault taken to Secure state from the more usual fault taken to the current security state. Signed-off-by: Peter Maydell --- target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++--- target/arm/translate.c | 10 ++++++-- 2 files changed, 60 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index a36f4b3d699..27e5f98bc73 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7561,6 +7561,25 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, return target_el; } +/* + * Return true if the v7M CPACR permits access to the FPU for the specified + * security state and privilege level. + */ +static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) +{ + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { + case 0: + case 2: /* UNPREDICTABLE: we treat like 0 */ + return false; + case 1: + return is_priv; + case 3: + return true; + default: + g_assert_not_reached(); + } +} + static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, ARMMMUIdx mmu_idx, bool ignfault) { @@ -8820,9 +8839,23 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; break; case EXCP_NOCP: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); - env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; + { + /* + * NOCP might be directed to something other than the current + * security state if this fault is because of NSACR; we indicate + * the target security state using exception.target_el. + */ + int target_secstate; + + if (env->exception.target_el == 3) { + target_secstate = M_REG_S; + } else { + target_secstate = env->v7m.secure; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secstate); + env->v7m.cfsr[target_secstate] |= R_V7M_CFSR_NOCP_MASK; break; + } case EXCP_INVSTATE: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; @@ -12756,6 +12789,22 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } + if (arm_feature(env, ARM_FEATURE_M)) { + /* CPACR can cause a NOCP UsageFault taken to current security state */ + if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { + return 1; + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { + if (!extract32(env->v7m.nsacr, 10, 1)) { + /* FP insns cause a NOCP UsageFault taken to Secure */ + return 3; + } + } + + return 0; + } + /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses @@ -12943,7 +12992,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { + || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); diff --git a/target/arm/translate.c b/target/arm/translate.c index d56488ec847..bb539111179 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3398,8 +3398,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) * for attempts to execute invalid vfp/neon encodings with FP disabled. */ if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + s->fp_excp_el); + } else { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } return 0; }