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[66.91.136.155]) by smtp.gmail.com with ESMTPSA id z22sm7025492pgv.23.2019.04.20.00.34.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Apr 2019 00:34:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2019 21:34:05 -1000 Message-Id: <20190420073442.7488-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190420073442.7488-1-richard.henderson@linaro.org> References: <20190420073442.7488-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 01/38] target/arm: Fill in .opc for cmtst_op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to fall back to integers if the tcg backend does not support comparisons in the given vece. Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 Reviewed-by: David Hildenbrand diff --git a/target/arm/translate.c b/target/arm/translate.c index d408e4d7ef..13e2dc6562 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6140,16 +6140,20 @@ static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) const GVecGen3 cmtst_op[4] = { { .fni4 = gen_helper_neon_tst_u8, .fniv = gen_cmtst_vec, + .opc = INDEX_op_cmp_vec, .vece = MO_8 }, { .fni4 = gen_helper_neon_tst_u16, .fniv = gen_cmtst_vec, + .opc = INDEX_op_cmp_vec, .vece = MO_16 }, { .fni4 = gen_cmtst_i32, .fniv = gen_cmtst_vec, + .opc = INDEX_op_cmp_vec, .vece = MO_32 }, { .fni8 = gen_cmtst_i64, .fniv = gen_cmtst_vec, .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .opc = INDEX_op_cmp_vec, .vece = MO_64 }, };