diff mbox series

[v3,01/50] trace: expand mem_info:size_shift to 3 bits

Message ID 20190614171200.21078-2-alex.bennee@linaro.org
State Superseded
Headers show
Series tcg plugin support | expand

Commit Message

Alex Bennée June 14, 2019, 5:11 p.m. UTC
From: "Emilio G. Cota" <cota@braap.org>


This will allow us to trace 16B-long memory accesses.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Emilio G. Cota <cota@braap.org>

---
 trace-events | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.20.1

Comments

Richard Henderson June 17, 2019, 2:12 a.m. UTC | #1
On 6/14/19 10:11 AM, Alex Bennée wrote:
> From: "Emilio G. Cota" <cota@braap.org>

> 

> This will allow us to trace 16B-long memory accesses.

> 

> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> Signed-off-by: Emilio G. Cota <cota@braap.org>

> ---

>  trace-events | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/trace-events b/trace-events

> index 844ee58dd9..037169aab3 100644

> --- a/trace-events

> +++ b/trace-events

> @@ -159,7 +159,7 @@ vcpu guest_cpu_reset(void)

>  # Access information can be parsed as:

>  #

>  # struct mem_info {

> -#     uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */

> +#     uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes */

>  #     bool    sign_extend: 1; /* sign-extended */

>  #     uint8_t endianness : 1; /* 0: little, 1: big */

>  #     bool    store      : 1; /* wheter it's a store operation */

> 


Well, 128B-long memory accesses.  But SVE supports 256B memory accesses
already.  So why not add one more bit now.


r~
Alex Bennée June 17, 2019, 8:22 a.m. UTC | #2
Richard Henderson <richard.henderson@linaro.org> writes:

> On 6/14/19 10:11 AM, Alex Bennée wrote:

>> From: "Emilio G. Cota" <cota@braap.org>

>>

>> This will allow us to trace 16B-long memory accesses.

>>

>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

>> Signed-off-by: Emilio G. Cota <cota@braap.org>

>> ---

>>  trace-events | 2 +-

>>  1 file changed, 1 insertion(+), 1 deletion(-)

>>

>> diff --git a/trace-events b/trace-events

>> index 844ee58dd9..037169aab3 100644

>> --- a/trace-events

>> +++ b/trace-events

>> @@ -159,7 +159,7 @@ vcpu guest_cpu_reset(void)

>>  # Access information can be parsed as:

>>  #

>>  # struct mem_info {

>> -#     uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */

>> +#     uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes */

>>  #     bool    sign_extend: 1; /* sign-extended */

>>  #     uint8_t endianness : 1; /* 0: little, 1: big */

>>  #     bool    store      : 1; /* wheter it's a store operation */

>>

>

> Well, 128B-long memory accesses.  But SVE supports 256B memory accesses

> already.  So why not add one more bit now.


Good point.

Do we have any architectures that do load/stores that are not power of
2? I guess the SVE non-faulting accesses are treated as a series of elem
size accesses.

>

>

> r~



--
Alex Bennée
Richard Henderson June 17, 2019, 11:29 p.m. UTC | #3
On 6/17/19 1:22 AM, Alex Bennée wrote:
> 

> Richard Henderson <richard.henderson@linaro.org> writes:

> 

>> On 6/14/19 10:11 AM, Alex Bennée wrote:

>>> From: "Emilio G. Cota" <cota@braap.org>

>>>

>>> This will allow us to trace 16B-long memory accesses.

>>>

>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

>>> Signed-off-by: Emilio G. Cota <cota@braap.org>

>>> ---

>>>  trace-events | 2 +-

>>>  1 file changed, 1 insertion(+), 1 deletion(-)

>>>

>>> diff --git a/trace-events b/trace-events

>>> index 844ee58dd9..037169aab3 100644

>>> --- a/trace-events

>>> +++ b/trace-events

>>> @@ -159,7 +159,7 @@ vcpu guest_cpu_reset(void)

>>>  # Access information can be parsed as:

>>>  #

>>>  # struct mem_info {

>>> -#     uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */

>>> +#     uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes */

>>>  #     bool    sign_extend: 1; /* sign-extended */

>>>  #     uint8_t endianness : 1; /* 0: little, 1: big */

>>>  #     bool    store      : 1; /* wheter it's a store operation */

>>>

>>

>> Well, 128B-long memory accesses.  But SVE supports 256B memory accesses

>> already.  So why not add one more bit now.

> 

> Good point.

> 

> Do we have any architectures that do load/stores that are not power of

> 2? I guess the SVE non-faulting accesses are treated as a series of elem

> size accesses.


Yes, non-faults are in addition predicated, so each element is considered
individually.

Even the SVE non-predicated load/stores can technically be considered a
sequence of byte operations.  Which, I suppose could be helpful, because SVE
can otherwise be configured to do non-power-of-2 operations.


r~
diff mbox series

Patch

diff --git a/trace-events b/trace-events
index 844ee58dd9..037169aab3 100644
--- a/trace-events
+++ b/trace-events
@@ -159,7 +159,7 @@  vcpu guest_cpu_reset(void)
 # Access information can be parsed as:
 #
 # struct mem_info {
-#     uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */
+#     uint8_t size_shift : 3; /* interpreted as "1 << size_shift" bytes */
 #     bool    sign_extend: 1; /* sign-extended */
 #     uint8_t endianness : 1; /* 0: little, 1: big */
 #     bool    store      : 1; /* wheter it's a store operation */