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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v1 2/9] target/arm: handle A-profile T32 semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , "open list:ARM TCG CPUs" , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 259c4669b4c..6157e9f52fc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10907,6 +10907,24 @@ static inline void gen_thumb_bkpt(DisasContext *s, int imm8) gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); } +/* + * Thumb SWI. On A-profile CPUs this may be a semihosting call. + */ +static inline void gen_thumb_swi(DisasContext *s, int imm8) +{ + if (semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm8 == 0xab)) { + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + return; + } + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = imm8; + s->base.is_jmp = DISAS_SWI; +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11658,10 +11676,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto undef; if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; + /* swi/svc */ + gen_thumb_swi(s, extract32(insn, 0, 8)); break; } /* generate a conditional jump to next instruction */