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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v2 3/5] target/arm: handle A-profile A32 semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API --- target/arm/translate.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 673994ed1a1..03396a1dde3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7683,6 +7683,22 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } +static inline void gen_arm_swi(DisasContext *s, int imm24) +{ + if (semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm24 == 0x123456)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + return; + } + + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = imm24; + s->base.is_jmp = DISAS_SWI; +} + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -9230,9 +9246,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; case 0xf: /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 24); - s->base.is_jmp = DISAS_SWI; + gen_arm_swi(s, extract32(insn, 0, 24)); break; default: illegal_op: