From patchwork Wed Sep 25 14:32:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 174361 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp735848ill; Wed, 25 Sep 2019 07:49:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxXOqDY6o3WeM6R1T4YO6CGjqAKBnFYT56Wzm5qRIjBZE1xykeJna8GBhyzjzb1q8W/9V/Y X-Received: by 2002:ae9:dd07:: with SMTP id r7mr4000349qkf.248.1569422944343; Wed, 25 Sep 2019 07:49:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569422944; cv=none; d=google.com; s=arc-20160816; b=yBvyGu0SNP9gV1PeyHG6sH2+jsnF0Myd3zgHl+D7uY0Ohc6rBMYD9+KnZ7GHe7dDme 9jPC/KQ/7h5zmhDVO22nZ56NdLilcSBhayNLtnILiYvKcibcCAaQO2abprSjBVjRKzM1 RsB1Jn0gbeZWMo5d3vW6FQw+l8Gz9U14S8MeVkQ82SDS+W3aE0ksKRxgujb4q+XLfOBB TMKAQhuFm38BkgjFkkXndY67NJbJ6o288NpTK6xsCqrlTBILghWq11tszMysFyODxkit yycSOYJeE7EsShhmgZ5qfXwf5hr/grqNN5JFN1K5p+ry9jdv1XfKqZw27IlohY6QlK8z U/iQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=u4X8CvYyyuAzWNkrfc9Pn6LFwcjz7veY1JOpwQY9I/U=; b=dFGVVXqt9GE2drxoOHikw4ei1GGWUDHg5xx+77ZJLjmQvHjVfe3zxoy5MvdJ5mb3OD bTNARhNwKlHZNodR1M0uYaLogwX3R0TYXhtDI+QWr17prWxN78bDtE6H1wIyRERWlNZ4 9wU65RU5AXyme2kC5RJXtTKgfJtxumUk4MviC7S5Yeu7uAI1vd7YLuVfnNZXXcHxpMKq wMM4UwkguaDIDcKinvNBsWhTpHf00P0DKz1Rwo9fLxE36N9sMiGHaZkkVRoVqmWdHqch pnwE5A1MM6A2+QiwonOK6Ji2ySPkuD7T5EvKAn88fr/CST6VO0Tv0sSraZqZgViTIubS +E1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b50si3872017qtc.62.2019.09.25.07.49.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Sep 2019 07:49:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:53116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD8bH-0001Aa-K0 for patch@linaro.org; Wed, 25 Sep 2019 10:49:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52617) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD8N7-0004A7-Dt for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD8N6-0001EP-0g for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:25 -0400 Received: from 4.mo3.mail-out.ovh.net ([178.33.46.10]:43796) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD8N5-0001Dm-RZ for qemu-devel@nongnu.org; Wed, 25 Sep 2019 10:34:23 -0400 Received: from player786.ha.ovh.net (unknown [10.108.35.90]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 42BC1226A0C for ; Wed, 25 Sep 2019 16:34:19 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player786.ha.ovh.net (Postfix) with ESMTPSA id 50F72A4D3F2D; Wed, 25 Sep 2019 14:34:13 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Subject: [PATCH v2 11/23] hw: wdt_aspeed: Add AST2600 support Date: Wed, 25 Sep 2019 16:32:36 +0200 Message-Id: <20190925143248.10000-12-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190925143248.10000-1-clg@kaod.org> References: <20190925143248.10000-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 8857173092676700945 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrfedvgdejkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.46.10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley [clg: - reworked model integration into new object class ] Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 2 +- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ba5bbb53e1a1..b427f2668a8a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -27,7 +27,7 @@ #include "hw/sd/aspeed_sdhci.h" #define ASPEED_SPIS_NUM 2 -#define ASPEED_WDTS_NUM 3 +#define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 2 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 796342764e2e..dfedd7662dd1 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -18,6 +18,7 @@ OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" #define ASPEED_WDT_REGS_MAX (0x20 / 4) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index fc0e6c486a70..145be6f99ce2 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -40,12 +40,14 @@ #define WDT_DRIVE_TYPE_MASK (0xFF << 24) #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) +#define WDT_RESET_MASK1 (0x1c / 4) #define WDT_TIMEOUT_STATUS (0x10 / 4) #define WDT_TIMEOUT_CLEAR (0x14 / 4) #define WDT_RESTART_MAGIC 0x4755 +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) #define SCU_RESET_CONTROL1 (0x04 / 4) #define SCU_RESET_SDRAM BIT(0) @@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) return s->regs[WDT_CTRL]; case WDT_RESET_WIDTH: return s->regs[WDT_RESET_WIDTH]; + case WDT_RESET_MASK1: + return s->regs[WDT_RESET_MASK1]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; break; + case WDT_RESET_MASK1: + /* TODO: implement */ + s->regs[WDT_RESET_MASK1] = data; + break; + case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info = { .class_init = aspeed_2500_wdt_class_init, }; +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); + + dc->desc = "ASPEED 2600 Watchdog Controller"; + awc->offset = 0x40; + awc->ext_pulse_width_mask = 0xfffff; /* TODO */ + awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; +} + +static const TypeInfo aspeed_2600_wdt_info = { + .name = TYPE_ASPEED_2600_WDT, + .parent = TYPE_ASPEED_WDT, + .instance_size = sizeof(AspeedWDTState), + .class_init = aspeed_2600_wdt_class_init, +}; + static void wdt_aspeed_register_types(void) { watchdog_add_model(&model); type_register_static(&aspeed_wdt_info); type_register_static(&aspeed_2400_wdt_info); type_register_static(&aspeed_2500_wdt_info); + type_register_static(&aspeed_2600_wdt_info); } type_init(wdt_aspeed_register_types)