From patchwork Wed Oct 23 15:00:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177307 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp885461ill; Wed, 23 Oct 2019 08:30:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwj84wYY9mx1pD/uNaY+6Q7Mza+2ABF+bCexe1pZ0/l37Y8mMZW0DLnNdjopaEbnbTOE446 X-Received: by 2002:a05:6402:13d6:: with SMTP id a22mr38208400edx.165.1571844635570; Wed, 23 Oct 2019 08:30:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844635; cv=none; d=google.com; s=arc-20160816; b=e2nqMG1mLz2VTemvLKg7RWSl8t3QsBAwZzfr0lskV7TapWvUdrwKJgitjfc4c/WFjH Hr/41BBoSe53cest4LYI9vGVNBnhxw1NV+OqLE62foUAOwbFr/epMuxsVgeBamLKKws4 paDjzsFnDW5aHKibQlzs4yOb3oLeRXz1oPHBxB+qQLnhMAjMr1/ZSBY1CoIj2VzPqv6r xWjYJjEs4ucl2gqyWnHFE2ZZYUZtaVfjwyYOZFEdkkfqQjhKuWQ2ZssSody/sPnaunnS +IZK3ljXJi6y4m/HpVdoLO2kZrd/7Ja3Kus7KKDfIHS2bDakQ2af9hNBiK1a60cFuo9D Sx8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/TI4mK10x/uGohRoaKTTXXODiX4sOLe+8x03viKmFL4=; b=q8ndMfOL43l6Yl60IIhqe88swKjlmo8Zh6B71uZdHxmuRDvyQCwrT/mGxtBo3GcDZR RGsw0hDVUfhB3ePrl+VbrEFyD5ezL5U7+epzYyGBk3FrNW4hsLFFURtLyhjvfUU4tMYY bUuG40VhxMAGX3J0d8Jrgad6p60it+BZxLYIOQI155pp8qyjeJjtr22ZwbT5VlJMuBVG srdvd4mgUuwsZwBpcQaF/qcuW2WAaWEenPDoDgeuhyYty9EvS8mcG8urAp5MzrXqTech 4lQssLkg/jATX9h2M+2zR5Y027Kw1/Rv9t0cKlaj6nZTzk1ZTaghU18yX64rOFAWI6Lo cRGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jVI3tStE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u14si14531096edq.167.2019.10.23.08.30.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Oct 2019 08:30:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jVI3tStE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNIan-0007UW-Lm for patch@linaro.org; Wed, 23 Oct 2019 11:30:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35267) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNI8u-00089i-FZ for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iNI8r-0001Fy-Gh for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:44 -0400 Received: from mail-qt1-x843.google.com ([2607:f8b0:4864:20::843]:37771) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iNI8r-0000zG-B1 for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:41 -0400 Received: by mail-qt1-x843.google.com with SMTP id g50so18581399qtb.4 for ; Wed, 23 Oct 2019 08:01:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/TI4mK10x/uGohRoaKTTXXODiX4sOLe+8x03viKmFL4=; b=jVI3tStENkvrA0RTOIuhunlVcBItLkEW8bl7Ub8R+s1Syd5MrrOssSNqo4Mj3jJIIt MR6EE2acY7++XYPZkd+mno+WKZCPen95AYSPSIfiy4/IZA2qiOZupE+37VQDDEWhv8fh amkEzk+Bce30G0Pd4bc0YF5QsHD/Pvr+de19yM7y/uv0cV6NVLi3eOonPm5j0B3zpCXR M7RKRV0viLcaROuIestq8Eh6X+H8IwtkmVPZbshoddECWVcFUNruRgdgDzjyBUjuuyXF ul6Ewg4U2CUk9Up+ohpZgilLRwnlQgVtEuayHcNZOrWypgDQJC2Ip0t+PSr9IbK3PXKw P/EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/TI4mK10x/uGohRoaKTTXXODiX4sOLe+8x03viKmFL4=; b=fc01zF96ImoKxi5L8eqE/lRKFt6s2G4y8Mk592fQVUt5cZ4r7tkogqLxDokSjnm2dR AMvIPr3u/KHVN2xMeToemhPem2P81/v0q8BOsshvabdcRFxO84DiRw+HKJCdQNSXRZ3H Pb9v1hI//zoTBVEkAy0tWlWfxWb/4YOhRyB5AA8SmBaxuGyTyzYYxZw+VHVp0tF4pUv+ hrmY9aU5imjO+2ULxAw4r/8bNfldFKaw9DdTSUx8ciluqcshQiUGAt9GeUYIldmU32K0 A1lKr9PbzT9SKX9W5k4qsoXm0IAuwVg859VWlyScO0RJVjuoVZ0H0DqZNTuSn4txjFOt 54uA== X-Gm-Message-State: APjAAAWHwsLacCi1JdZDndro9SFFLbci8zPAXTE8Fy0gUwmuc+nnnmyf xQ1ugWu0B1RSdVq30u72LH4ozUSzhVg= X-Received: by 2002:ac8:51c9:: with SMTP id d9mr9823200qtn.48.1571842862867; Wed, 23 Oct 2019 08:01:02 -0700 (PDT) Received: from localhost.localdomain (198-4-20-64.static.cosmoweb.net. [64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 01/24] target/arm: Split out rebuild_hflags_common Date: Wed, 23 Oct 2019 11:00:34 -0400 Message-Id: <20191023150057.25731-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 ++++++++++++++++++----------- target/arm/helper.c | 26 +++++++++++++++++++------- 2 files changed, 37 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..ad79a6153b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3140,15 +3143,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3165,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3181,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3201,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..8829d91ae1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11054,6 +11054,22 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11145,7 +11161,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11153,9 +11169,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { if (is_a64(env)) { if (env->pstate & PSTATE_SS) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); @@ -11166,10 +11182,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);