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[209.51.188.17]) by mx.google.com with ESMTPS id 145si2179371qkd.65.2019.11.13.14.24.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Nov 2019 14:24:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=KSJ9+PCG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iV147-0007iP-UC for patch@linaro.org; Wed, 13 Nov 2019 17:24:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34946) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iV0tN-0001sW-1T for qemu-devel@nongnu.org; Wed, 13 Nov 2019 17:13:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iV0tL-0001JV-0V for qemu-devel@nongnu.org; Wed, 13 Nov 2019 17:13:36 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:34002) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iV0tE-0001G0-K8; Wed, 13 Nov 2019 17:13:28 -0500 Received: by mail-pl1-x644.google.com with SMTP id h13so1669042plr.1; Wed, 13 Nov 2019 14:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nAP5XJXdKxaozCcpOcXkIdrUjuBLz94yxW3NObWQlgM=; b=KSJ9+PCGE7qR0mmVCze0s+sM2HIzUzZ2VQXrgmI8YGkl/K4jObRNkEgMXQtLXIA+Em KlMRApyxFOkwr4yu5kGYDWmpyo0dbdy8+CHRemXlSryWMjZ09U5u5gAHEIitcquv1MIN JuwRPSJ9nHFy5ex1eyftCtooJJlrHd1sj2bNlkJqWSxnQrwLeMynca1jiClM6zFOVID2 +xCwxza1ArFXBpnKM2FHL3OnyNjDI7k5PldE2ncsRgiy2RVNFHYoSufKannhIRQLVvyQ PK/TVgdK1Acg0veLH0X5KmMgJlpW947o7cSXJTbNun8vKfLxdYhj8mLlLOqYI9sezHFa u+Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nAP5XJXdKxaozCcpOcXkIdrUjuBLz94yxW3NObWQlgM=; b=AGYUWAGmYHAXxuvayhb/ZAnVMOBV2WPTvaII6CcwQ87Gd54WTVW/ZT8W3TJL42HxcA Ag66WoXGTl3a+9PDudwixlxsqHt7U0jgoiP47c4xc/W/xZkEbCiq8IPQN1c6RAFyN2nM NCob1XPopzrkM8UKxSlvanWqUqBxGKyqYoL4sPFOe5Woi02UyqfZ7tff0a69dHi0Hq9U Wz9JRCzPuRr/JFa9DbezQBnPB+mNd5lQ/EKVLe8fD4oufvRnWqe4RnQN7h5OT5nvaBov Nf8XAiAbW/zrFXxV6pda/9qYBxBZ97KtwjLVa4258EvGeoABO2ioA+RuNe7VJaD9Q6Ug 65/Q== X-Gm-Message-State: APjAAAV0W9zZBeCv/13A48HF+DBCLyf7oBoRHzoGRPHSs9UQ2uJXJD6A +aF4QMKGTNzC1Sj+0m51xOE= X-Received: by 2002:a17:902:6f01:: with SMTP id w1mr6355065plk.35.1573683207515; Wed, 13 Nov 2019 14:13:27 -0800 (PST) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id w69sm5252005pfc.164.2019.11.13.14.13.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2019 14:13:27 -0800 (PST) From: Joel Stanley To: Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Subject: [PATCH v3 4/4] watchdog/aspeed: Fix AST2600 frequency behaviour Date: Thu, 14 Nov 2019 08:43:01 +1030 Message-Id: <20191113221301.8768-5-joel@jms.id.au> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191113221301.8768-1-joel@jms.id.au> References: <20191113221301.8768-1-joel@jms.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AST2600 control register sneakily changed the meaning of bit 4 without anyone noticing. It no longer controls the 1MHz vs APB clock select, and instead always runs at 1MHz. The AST2500 was always 1MHz too, but it retained bit 4, making it read only. We can model both using the same fixed 1MHz calculation. Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support") Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley --- v2: Fix Fixes line in commit message --- hw/watchdog/wdt_aspeed.c | 21 +++++++++++++++++---- include/hw/watchdog/wdt_aspeed.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) -- 2.24.0 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index d283d07d6546..122aa8daaadf 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -93,11 +93,11 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) } -static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) +static void aspeed_wdt_reload(AspeedWDTState *s) { uint64_t reload; - if (pclk) { + if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, s->pclk_freq); } else { @@ -109,6 +109,16 @@ static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) } } +static void aspeed_wdt_reload_1mhz(AspeedWDTState *s) +{ + uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; + + if (aspeed_wdt_is_enabled(s)) { + timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); + } +} + + static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, unsigned size) { @@ -130,13 +140,13 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, case WDT_RESTART: if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; - aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); + awc->wdt_reload(s); } break; case WDT_CTRL: if (enable && !aspeed_wdt_is_enabled(s)) { s->regs[WDT_CTRL] = data; - aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); + awc->wdt_reload(s); } else if (!enable && aspeed_wdt_is_enabled(s)) { s->regs[WDT_CTRL] = data; timer_del(s->timer); @@ -283,6 +293,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) awc->offset = 0x20; awc->ext_pulse_width_mask = 0xff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; + awc->wdt_reload = aspeed_wdt_reload; } static const TypeInfo aspeed_2400_wdt_info = { @@ -317,6 +328,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) awc->ext_pulse_width_mask = 0xfffff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; + awc->wdt_reload = aspeed_wdt_reload_1mhz; } static const TypeInfo aspeed_2500_wdt_info = { @@ -336,6 +348,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) awc->ext_pulse_width_mask = 0xfffff; /* TODO */ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; + awc->wdt_reload = aspeed_wdt_reload_1mhz; } static const TypeInfo aspeed_2600_wdt_info = { diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index dfedd7662dd1..819c22993a6e 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -47,6 +47,7 @@ typedef struct AspeedWDTClass { uint32_t ext_pulse_width_mask; uint32_t reset_ctrl_reg; void (*reset_pulse)(AspeedWDTState *s, uint32_t property); + void (*wdt_reload)(AspeedWDTState *s); } AspeedWDTClass; #endif /* WDT_ASPEED_H */