From patchwork Thu Feb 13 14:41:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 183371 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp624788ile; Thu, 13 Feb 2020 06:58:45 -0800 (PST) X-Google-Smtp-Source: APXvYqxh+BUMTaqzabBq3SNFFB4iPPH3Ftsy/rd9JLgDr8SKPlYmp2WbN8yiLrjRxk6CF/3aDs6y X-Received: by 2002:ac8:669a:: with SMTP id d26mr5145857qtp.304.1581605925223; Thu, 13 Feb 2020 06:58:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581605925; cv=none; d=google.com; s=arc-20160816; b=OaWAO8jj4sN9rCqpgXPpIjdF+r9dusGIAKJ+kapj+6EcWJTGMoz3N+vB2GyQKwcg25 SJS8u6xQ6V67wysRGDq3nRhwNy8CdAhLmJWI89yfgoUedTqZdEFu/17VxcCSx1OtJEkP Jr9+O1fWnxqVH8vfd8RTpqkOuK5mfKXNLN4tmYYqf2DVBFFPnLAJfpmI7Qon9jlOZo9M /INKgBclF0VCmPbzDJFR/WQ2gP+TbiLe2ip6egUNy+qrCp2oVeK53l6Wuw41nEoGDZFH ZsqTai4Kd5sbK78f1fyD2BL53OPBRKJBF0iJ6PrsxGyKQLsMsDx1sAeKADGyWbmVSOGS 4FJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=61vVlMzzHiCFs/xussXaIHw4eQnhk5SVWAOHn9JeXe0=; b=fx3LZcjhhAPrNL8G83nMSa5O9Fc06MVBqGCUF7V3gGhbdL7pUYeGuDxxIQIzAUsFD8 YCt/0PLzn1yZOooWVUe7LUK91U2cIsQn1+dj2rvZuNUF9/g+lM5VegAHK69TPC5HtXPw 3eWHjh+upkHGCzO/WKhV3fQOfiRsaIA4tz5fhh6chlDN9Km28DYFNdJlpJRjTNfxroBK +4AjZlkiZnQEhKx/sYisknCa8GI7NQBWwcr+clNIGCeHKeH5Vlq/dBQODzBLWUqhs8y1 4+f2X4T4xEJfW5kGcz0Dg2TFnLNNBhvv8dvk+9Xk1snnyJm2QjMtEZimOHLEVAJ7GEyp /rpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKEKXxOw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x33si1326939qtc.180.2020.02.13.06.58.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Feb 2020 06:58:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKEKXxOw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2Fwy-000132-Ny for patch@linaro.org; Thu, 13 Feb 2020 09:58:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60229) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2Fgx-0004MY-5R for qemu-devel@nongnu.org; Thu, 13 Feb 2020 09:42:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2Fgs-0001oW-Ql for qemu-devel@nongnu.org; Thu, 13 Feb 2020 09:42:11 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:55646) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2Fgs-0001lt-JY for qemu-devel@nongnu.org; Thu, 13 Feb 2020 09:42:06 -0500 Received: by mail-wm1-x32e.google.com with SMTP id q9so6527353wmj.5 for ; Thu, 13 Feb 2020 06:42:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=61vVlMzzHiCFs/xussXaIHw4eQnhk5SVWAOHn9JeXe0=; b=bKEKXxOwXTmrLsZBKZzmVTCFPJVs3XNHE4i3w97ZS18Fj3JYX8Tf6HsPnC+LGDaTt0 0DJGTuxVNrPKj3d2zBBDq6KlfInfrGeBcg7PORYTplY6KVGtnpUydISTLO1/JBYijzqd X7pqPn+h8XEKRmfUPr6T6TogpF3y4oSDPwz1fHDGBgDymu4jp2o/hYTyw6mThXVykpen 0FY2leaAwuZ+dK7eilANtH8z4LkW/5DKfZS3amBi6Z0KNfFqPP3wsxPR8BmyQMg6cdrx fhNUmwB7GB8Xf3qK5RuZICBgjtIPeiS8YMQuoHQgkQygG5iF1lkrg192rLeSREssfYLO U8mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=61vVlMzzHiCFs/xussXaIHw4eQnhk5SVWAOHn9JeXe0=; b=LhkBTZkR23wSRgx0BhLZKEYGKCScOlsntW39lbRg0N9j3pWceH7I0g3zLaHdpQEzdp /7rET0pH/vU59wFwGYdsLLrmMOo7tAv1O80BeWg1rMIPLE9lsmMcb3Q2pC/4eGiAt792 iZBmmo8zEesx520LhADQreCHSeSqVRTrJvxMvvwj2J35MAm3qtETIc89RkfZwmvhX582 KjjXhQjmYffppWwx2Wxqr/wW84SHglqOvF3uI7Yw6d7JDRqfcSe8u7i+1f7arkqHh+cJ 3J4IcPFn4MZsyk17vF0v12lYeaAwFkMqLbmQpKR4kHwXhk+wkLWk6PB72VceBBFrviJ5 zDkA== X-Gm-Message-State: APjAAAXqj4XiiXUKCXHiMUuSiqahK67o/9cammmu+JCvk+T9W2gsTMQG 3IWMhLqX4BqyPjH5C6p89tRaT9an+lI= X-Received: by 2002:a1c:7c11:: with SMTP id x17mr6622499wmc.168.1581604924417; Thu, 13 Feb 2020 06:42:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e22sm3362454wme.45.2020.02.13.06.42.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 06:42:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/46] target/arm: Move LOR regdefs to file scope Date: Thu, 13 Feb 2020 14:41:12 +0000 Message-Id: <20200213144145.818-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org> References: <20200213144145.818-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson For static const regdefs, file scope is preferred. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20200208125816.14954-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index bfd6c0d04bd..e4f17c7e839 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6334,6 +6334,35 @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7568,34 +7597,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] = { - { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, - .access = PL1_R, .accessfn = access_lorid, - .type = ARM_CP_CONST, .resetvalue = 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); }