From patchwork Sat Apr 18 16:19:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 185566 Delivered-To: patch@linaro.org Received: by 2002:a92:3d9a:0:0:0:0:0 with SMTP id k26csp1908500ilf; Sat, 18 Apr 2020 09:29:01 -0700 (PDT) X-Google-Smtp-Source: APiQypIgadah2e1Vh2L3JUO8PRSngM5wuCdSDBg3xT16+vIWuvJvRGKqOzplcbFoIYePjrPyMc7D X-Received: by 2002:aed:3ea5:: with SMTP id n34mr8396918qtf.60.1587227341739; Sat, 18 Apr 2020 09:29:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1587227341; cv=none; d=google.com; s=arc-20160816; b=Bde44NgXprlS3KV7IvBhyWsRuW1qg9rt5kMiV3qErNlnNb5z1AuPIOTq6Pf4qdWj6p lEj3VH88l8zwG2NJVOcydOb0rM695UZ8q/wpGrHljfQaJsi91DV7vkX3UpqwvHhzwfep J1HA8XdXWCyxnrXMDMdsR/ZnFbMzTQUTq5kVf+d3jtyT1+oyGhdJ671XQw6WBYtB2jkS VlZZi1Fc+5CIhegkAXz6q84BK+0KoaarsqY7UJqO/13kRJuU80jPl8UNKxBrN/e8M+tq pBpveExS6z07d5F1CrpHrc9mYB6/xqc7ZKznhHWz2QWkyD1ZaJC1EpAkphb3QTV+iEH2 /sSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rhrw9pekgEH5BB8vddUs+wUSUQ/QGWXX4jtEuHwbb9o=; b=HYA3idRfY1xmLOrhJ7yLaEb8/B8CEP4oHbrltz5i4PnKXNzFpIipP2jAZsc1I91IfM zN6kYDHpNulztBSD3VMiNOvPYrU6qq/VH0QCFUJQlDW3dToqrT82mlOm077JgQTePoMt h3we1JaqOT7ZiGiW3pRYi1ahp854gINVh6C34MKx4cFasKiP+sKS19E64sRjLLyxX0UO tzov3PMLGWwSCs5uKCnPmykYKlbVtenqsdOfMyHxZCrctAEN3G/tp62eITyw+bn6uxOn UP+5nvIJJd/qR+opIBsN6hynH92ZzAzETErIxe2xV2Z4PtxTQsJKrBAu97Kfny1IBjJR Y06g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mFGtyIm8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n197si6189800qke.152.2020.04.18.09.29.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Apr 2020 09:29:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mFGtyIm8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPqKz-00018h-9Q for patch@linaro.org; Sat, 18 Apr 2020 12:29:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48233) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPqBs-0004N8-Ib for qemu-devel@nongnu.org; Sat, 18 Apr 2020 12:19:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jPqBo-0005PW-Qf for qemu-devel@nongnu.org; Sat, 18 Apr 2020 12:19:36 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:43045) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jPqBo-0005Mj-KA for qemu-devel@nongnu.org; Sat, 18 Apr 2020 12:19:32 -0400 Received: by mail-pg1-x542.google.com with SMTP id x26so2750874pgc.10 for ; Sat, 18 Apr 2020 09:19:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rhrw9pekgEH5BB8vddUs+wUSUQ/QGWXX4jtEuHwbb9o=; b=mFGtyIm8aXtwepM3X0K2kdrbPl/k3xePMM5pFou8hIqpRMnEE01dV0sDcCKL2EtuQ9 y2S/SmnkXMoa19g/UN9Q84cqpGl2Bf4iNXt+YfC/Z2aOY3tA6V8Z4c6iUVjIeGd3Xmp7 K6MArCQkx+ahlrYEJIIUetiWDVjemvvyRx/xZtA+Bn2A6/p6l6OPVzS/SLnU+5S6G0+8 yKmlHk63zlQWIAoCGObk+1FV+KMKUHwJn2mOJjCTZWHC5H4h5erFFLlhx9lzM0GrwnE1 lX+twH6qQeY8lQl9bkaufT8OugWhkojzCQ87tf7bWni0VMGKoYqSmAAruYIo6hd8ays9 CYJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rhrw9pekgEH5BB8vddUs+wUSUQ/QGWXX4jtEuHwbb9o=; b=d/9+yQM/KVUH2/LZ9ZcnsqOgJJreQlU05uXS8HKE0Yl6hHAhV93VM0hL+eBSnhpjAV ZMmdLMkB4zXs+OdrS5LgZj9eq0LvCehiDOfQoxDcM3n5DisrcxiQHsDGQ13l4HDdXklj EHoWx5iTk9/yxRQzUN6ZcogZa18nilGLWeABfabNCGmKOv6wXyDAR0Ja6Fk1Fo9HyUKv 2rN1+up7cOooNA/J2id2b+oOsCenNNA5DVY9wySTX7Lad6ctTntEOrpXOUyaBKa/gS/U A+4acgYa+FJcIRwkmKjFIWJy3X1QlGQI91GEqdx39Ll4laXFlvsbnIicwOjWDlNMkRZm w3+A== X-Gm-Message-State: AGi0PuZpWEpdAAGjH/fhS9MVdoiGUNxMb5b0xKdmx7ANBFkq7kx26uVQ HH9Rbsvthlof17ZRsQXrpusTu7Cn2eM= X-Received: by 2002:a05:6a00:5:: with SMTP id h5mr8727050pfk.57.1587226771076; Sat, 18 Apr 2020 09:19:31 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id i187sm22398382pfc.112.2020.04.18.09.19.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Apr 2020 09:19:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/16] tcg: Remove movi and dupi opcodes Date: Sat, 18 Apr 2020 09:19:09 -0700 Message-Id: <20200418161914.4387-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200418161914.4387-1-richard.henderson@linaro.org> References: <20200418161914.4387-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are now completely covered by mov from a TYPE_CONST temporary. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 --- tcg/aarch64/tcg-target.inc.c | 3 --- tcg/arm/tcg-target.inc.c | 1 - tcg/i386/tcg-target.inc.c | 3 --- tcg/mips/tcg-target.inc.c | 2 -- tcg/optimize.c | 4 ---- tcg/ppc/tcg-target.inc.c | 3 --- tcg/riscv/tcg-target.inc.c | 2 -- tcg/s390/tcg-target.inc.c | 2 -- tcg/sparc/tcg-target.inc.c | 2 -- tcg/tcg-op-vec.c | 1 - tcg/tcg.c | 18 +----------------- tcg/tci/tcg-target.inc.c | 2 -- 13 files changed, 1 insertion(+), 45 deletions(-) -- 2.20.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 7dee9b38f7..4a9cbf5426 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -45,7 +45,6 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) -DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) /* load/store */ @@ -110,7 +109,6 @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) -DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) /* load/store */ @@ -215,7 +213,6 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) -DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 843fd0ca69..7918aeb9d5 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2261,8 +2261,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); @@ -2467,7 +2465,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 6aa7757aac..b967499fa4 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2068,7 +2068,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ec083bddcf..320a4bddd1 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2678,8 +2678,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -2965,7 +2963,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 4d32ebc1df..09dc5a94fa 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2155,8 +2155,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/optimize.c b/tcg/optimize.c index dd5187be31..9a2c945dbe 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1099,10 +1099,6 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(mov): tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); break; - CASE_OP_32_64(movi): - case INDEX_op_dupi_vec: - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]); - break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index ee1f9227c1..fb390ad978 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -2967,8 +2967,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -3310,7 +3308,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, return; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 2bc0ba71f2..ec609272ad 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1606,8 +1606,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index b07e9ff7d6..f6b003a700 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -2310,8 +2310,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 65fddb310d..0808b79eee 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1591,8 +1591,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 655b3ae32d..6343046e18 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -83,7 +83,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_xor_vec: case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: diff --git a/tcg/tcg.c b/tcg/tcg.c index 59beb2bf29..adb71f16ae 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1463,7 +1463,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_goto_ptr; case INDEX_op_mov_i32: - case INDEX_op_movi_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: case INDEX_op_ld8u_i32: @@ -1557,7 +1556,6 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_REG_BITS == 32; case INDEX_op_mov_i64: - case INDEX_op_movi_i64: case INDEX_op_setcond_i64: case INDEX_op_brcond_i64: case INDEX_op_ld8u_i64: @@ -1663,7 +1661,6 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_vec: case INDEX_op_dup_vec: - case INDEX_op_dupi_vec: case INDEX_op_dupm_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: @@ -3447,7 +3444,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) } /* - * Specialized code generation for INDEX_op_movi_*. + * Specialized code generation for INDEX_op_mov_* with a constant. */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_life, @@ -3470,14 +3467,6 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, } } -static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) -{ - TCGTemp *ots = arg_temp(op->args[0]); - tcg_target_ulong val = op->args[1]; - - tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); -} - /* * Specialized code generation for INDEX_op_mov_*. */ @@ -4263,11 +4252,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; - case INDEX_op_movi_i32: - case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: - tcg_reg_alloc_movi(s, op); - break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 1f1639df0d..b796f4fc19 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -815,8 +815,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort();