diff --git a/riscv64.risu b/riscv64.risu
new file mode 100644
index 0000000..98141ab
--- /dev/null
+++ b/riscv64.risu
@@ -0,0 +1,141 @@
+# Input file for risugen defining RISC-V instructions
+.mode riscv
+@RV64I
+
+# x2 stack pointer, x3 global pointer, x4 thread pointer
+# These registers should be reserved for signal handler.
+
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+AUIPC RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+# Limit to current implementation, the base address register will be overide
+LB RISCV imm:12 rs1:5 000 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LH RISCV imm:12 rs1:5 001 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LW RISCV imm:12 rs1:5 010 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLTU  RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LD RISCV imm:12 rs1:5 011 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
