From patchwork Fri May 8 15:17:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186374 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp89958ill; Fri, 8 May 2020 08:32:00 -0700 (PDT) X-Google-Smtp-Source: APiQypL23ejFkJTXhpjFGks5s0KCibUWJIagir7yo76MNhKcDVRBmu27okAscPL04fYGVJNqp2N0 X-Received: by 2002:aed:34a5:: with SMTP id x34mr3417044qtd.216.1588951920587; Fri, 08 May 2020 08:32:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1588951920; cv=none; d=google.com; s=arc-20160816; b=B+pCNLw6lcgEYprh7qFNz1Uc8uHqmVu5r7nXa2hL2Lt8h6Ds9hlqzkUlDuQGOStJ7V w5BhBJxUEGrh0ExSN5RinXVqESMo0ah8ZLMzBxNbSmFmC9zMnZMXmqv0mVC4eh1/Mdvc P4ZZSBuOlQW9vTbij1mHgjDDEtsBCzC5XYKfHVsIG+ZDlFzPtye18GAQUhHkj9IEIHX4 D1zQhGN5LqNCY8++n40cEOFa1wj1GM1AAoxCvcfiqp1rGrz0eF2+Bqnuwzi1aMFOn676 +WXNtliJ1E5Pp6MuHVyxKoxE4H6Za6+aFgt9U2mSECKSjrsYaNEGWnbuREp+lZlF3VIO ptdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kyd75dQ6HSF4Bc6As5SxJ/ajmbJCQUS6r+6XFxFF4i4=; b=fgXOfEXifsDeVOO2yKYzVcqJ/ue/Zzi5f/ga4hnozn4arGmvISXBCmLjWtuGvNKpNB WB4/lV5qnwwcqZgNczbykWNC6cIXp7k8/q0VaIrpUEX4GVoJc+Eepf851JgJ6ziHw8Ta bqDuOJkesXookwPlPOJE9CSbCc2LIAmk1Att2UxRs51yuWJf3E1S+gY5DQC5iufqVMwB kheS7HVHr5I0BRMHr6MoaFKSEDEm5XQoyb/MsfR3BOy+iwM33ry5p+qd4fWcl7q/s58/ jvDWbunHFyQeNhQuEmnu18V1Wz1DOyWoufk34pr9yqwVM/kYoKA2tSOCk3NWNSlYPCNv 1bVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L2JtC1OH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:470:142::17]) by mx.google.com with ESMTPS id a21si1177796qtc.162.2020.05.08.08.32.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 May 2020 08:32:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) client-ip=2001:470:142::17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L2JtC1OH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:470:142::17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jX4yl-0001g0-UC for patch@linaro.org; Fri, 08 May 2020 11:31:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jX4lU-0006Cj-M7 for qemu-devel@nongnu.org; Fri, 08 May 2020 11:18:16 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:34388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jX4lQ-0003F2-Lj for qemu-devel@nongnu.org; Fri, 08 May 2020 11:18:16 -0400 Received: by mail-pl1-x642.google.com with SMTP id s10so856698plr.1 for ; Fri, 08 May 2020 08:18:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kyd75dQ6HSF4Bc6As5SxJ/ajmbJCQUS6r+6XFxFF4i4=; b=L2JtC1OHJja/JFbC8t/jwZOoHqQXOpAkJhI9MUtaF/romDh/Qb4I2eZA0KqKUY3GQ0 WZxHSlmgJWd4TSZVAQPVACGHU35+rpcXbouvanT+AnZNiDL1BI895cGZoJSc+ytKtRaN 1XR+7NguW2tlZ9mK0YsHVQ9ABRCL3oVPtlM0YQY8o6C9d4clPykot5lWH1fUAEMfVhPK b9NbHYfY7Ygo5Mf2HYtw4lA1pvEXIygfdaT6UfCOAHY2jgzuBidSdHpedTnohXLJCF8y gOuBaxDnjcmeFYvbt5ZTM/fk/TK0vHCGDywDVETJyzw6koecs7gdKTPJ/Ld9Sdz3mqlB h0Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kyd75dQ6HSF4Bc6As5SxJ/ajmbJCQUS6r+6XFxFF4i4=; b=Q6lnU97+zPechQLezyAoySmtvSrUk6XkHO7cff/2tVPSV+D4RbbQC+7u+U042fr7m9 /crzK7aIRZdG7RIY7GdLWny1awa4qntSjea3s7MMilCFUULRwNRzc/oVJOgCoV+EgbKr 2ZqzC513EOo7oquN2v7CeyEkbCXKwEL9p9WHiCGVH0s4/wxqyCr70qSsVGHZDX5W29BB jnbfB4NXHIWdZfUK9X9Sk7alBwYNxkDnfk1mvfwPPmFcCAVuR3dS2KxhJEYGl3ZsW08a xRxMq+QFUhzAJ5mJRqXVsZf7JhE7cDVs/LM2/xEeQs6eG3fFKXOIgRBGw3lduwKfff/E szXQ== X-Gm-Message-State: AGi0PuZN8/zpA7iFMdZKsVXEX6V118Ne1TvseKrKQ8nozv+8+2wJ15ZN M3z1FYXwlJbL8FsuDYGbgS59RlINIUc= X-Received: by 2002:a17:902:40a:: with SMTP id 10mr2901923ple.183.1588951090222; Fri, 08 May 2020 08:18:10 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id b5sm2125933pfb.190.2020.05.08.08.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2020 08:18:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/19] tcg: Add tcg_reg_alloc_dup2 Date: Fri, 8 May 2020 08:17:45 -0700 Message-Id: <20200508151747.6166-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200508151747.6166-1-richard.henderson@linaro.org> References: <20200508151747.6166-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) -- 2.20.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 18ebcc98f6..e8fe2d580b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3908,6 +3908,91 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } } +static void tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life = op->life; + TCGTemp *ots, *itsl, *itsh; + TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; + + /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_debug_assert(TCGOP_VECE(op) == MO_64); + + ots = arg_temp(op->args[0]); + itsl = arg_temp(op->args[1]); + itsh = arg_temp(op->args[2]); + + /* ENV should not be modified. */ + tcg_debug_assert(!temp_readonly(ots)); + + /* Allocate the output register now. */ + if (ots->val_type != TEMP_VAL_REG) { + TCGRegSet allocated_regs = s->reserved_regs; + TCGRegSet dup_out_regs = + tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; + + /* Make sure to not spill the input registers. */ + if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsl->reg); + } + if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsh->reg); + } + + ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type = TEMP_VAL_REG; + ots->mem_coherent = 0; + s->reg_to_temp[ots->reg] = ots; + } + + /* Promote dup2 of immediates to dupi_vec. */ + if (itsl->val_type == TEMP_VAL_CONST && + itsh->val_type == TEMP_VAL_CONST) { + tcg_out_dupi_vec(s, vtype, ots->reg, + (uint32_t)itsl->val | ((uint64_t)itsh->val << 32)); + goto done; + } + + /* If the two inputs form one 64-bit value, try dupm_vec. */ + if (itsl + 1 == itsh && + itsl->base_type == TCG_TYPE_I64 && + itsh->base_type == TCG_TYPE_I64) { + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } +#ifdef HOST_WORDS_BIGENDIAN + TCGTemp *its = itsh; +#else + TCGTemp *its = itsl; +#endif + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, + its->mem_base->reg, its->mem_offset)) { + goto done; + } + } + + /* Fall back to generic expansion. */ + tcg_reg_alloc_op(s, op); + return; + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, itsl); + } + if (IS_DEAD_ARG(2)) { + temp_dead(s, itsh); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); + } else if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } +} + #ifdef TCG_TARGET_STACK_GROWSUP #define STACK_DIR(x) (-(x)) #else @@ -4299,6 +4384,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; + case INDEX_op_dup2_vec: + tcg_reg_alloc_dup2(s, op); + break; case INDEX_op_insn_start: if (num_insns >= 0) { size_t off = tcg_current_code_size(s);