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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s14sm3738327wmh.18.2020.05.15.07.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2020 07:21:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/10] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree Date: Fri, 15 May 2020 15:20:50 +0100 Message-Id: <20200515142056.21346-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200515142056.21346-1-peter.maydell@linaro.org> References: <20200515142056.21346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree. (These are the last instructions in the group that are vectorized; the rest all require looping over each element.) Signed-off-by: Peter Maydell --- target/arm/neon-dp.decode | 63 +++++++++++++++++++++++++++++++++ target/arm/translate-neon.inc.c | 7 ++++ target/arm/translate.c | 52 +++------------------------ 3 files changed, 74 insertions(+), 48 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 648812395f1..3ed10d1524e 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -233,6 +233,69 @@ VSHR_U_2sh 1111 001 1 1 . 01 .... .... 0000 0 . . 1 .... \ VSHR_U_2sh 1111 001 1 1 . 001 ... .... 0000 0 . . 1 .... \ @2reg_shift size=0 shift=%neon_rshift_i3 +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VSRA_S_2sh 1111 001 0 1 . 1 ..... .... 0001 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VSRA_S_2sh 1111 001 0 1 . 01 .... .... 0001 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VSRA_S_2sh 1111 001 0 1 . 001 ... .... 0001 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VSRA_U_2sh 1111 001 1 1 . 1 ..... .... 0001 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VSRA_U_2sh 1111 001 1 1 . 01 .... .... 0001 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VSRA_U_2sh 1111 001 1 1 . 001 ... .... 0001 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VRSHR_S_2sh 1111 001 0 1 . 1 ..... .... 0010 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VRSHR_S_2sh 1111 001 0 1 . 01 .... .... 0010 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VRSHR_S_2sh 1111 001 0 1 . 001 ... .... 0010 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VRSHR_U_2sh 1111 001 1 1 . 1 ..... .... 0010 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VRSHR_U_2sh 1111 001 1 1 . 01 .... .... 0010 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VRSHR_U_2sh 1111 001 1 1 . 001 ... .... 0010 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VRSRA_S_2sh 1111 001 0 1 . 1 ..... .... 0011 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VRSRA_S_2sh 1111 001 0 1 . 01 .... .... 0011 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VRSRA_S_2sh 1111 001 0 1 . 001 ... .... 0011 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VRSRA_U_2sh 1111 001 1 1 . 1 ..... .... 0011 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VRSRA_U_2sh 1111 001 1 1 . 01 .... .... 0011 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VRSRA_U_2sh 1111 001 1 1 . 001 ... .... 0011 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + +VSRI_2sh 1111 001 1 1 . ...... .... 0100 1 . . 1 .... \ + @2reg_shift size=3 shift=%neon_rshift_i6 +VSRI_2sh 1111 001 1 1 . 1 ..... .... 0100 0 . . 1 .... \ + @2reg_shift size=2 shift=%neon_rshift_i5 +VSRI_2sh 1111 001 1 1 . 01 .... .... 0100 0 . . 1 .... \ + @2reg_shift size=1 shift=%neon_rshift_i4 +VSRI_2sh 1111 001 1 1 . 001 ... .... 0100 0 . . 1 .... \ + @2reg_shift size=0 shift=%neon_rshift_i3 + VSHL_2sh 1111 001 0 1 . shift:6 .... 0101 1 . . 1 .... \ @2reg_shift size=3 VSHL_2sh 1111 001 0 1 . 1 shift:5 .... 0101 0 . . 1 .... \ diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c index 0475696835f..f4d42683aea 100644 --- a/target/arm/translate-neon.inc.c +++ b/target/arm/translate-neon.inc.c @@ -1366,6 +1366,13 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) DO_2SH(VSHL, tcg_gen_gvec_shli) DO_2SH(VSLI, gen_gvec_sli) +DO_2SH(VSRI, gen_gvec_sri) +DO_2SH(VSRA_S, gen_gvec_ssra) +DO_2SH(VSRA_U, gen_gvec_usra) +DO_2SH(VRSHR_S, gen_gvec_srshr) +DO_2SH(VRSHR_U, gen_gvec_urshr) +DO_2SH(VRSRA_S, gen_gvec_srsra) +DO_2SH(VRSRA_U, gen_gvec_ursra) static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) { diff --git a/target/arm/translate.c b/target/arm/translate.c index f2ccab1b21c..4a55986aad9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5297,6 +5297,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) switch (op) { case 0: /* VSHR */ + case 1: /* VSRA */ + case 2: /* VRSHR */ + case 3: /* VRSRA */ + case 4: /* VSRI */ case 5: /* VSHL, VSLI */ return 1; /* handled by decodetree */ default: @@ -5330,54 +5334,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) shift = shift - (1 << (size + 3)); } - switch (op) { - case 1: /* VSRA */ - /* Right shift comes here negative. */ - shift = -shift; - if (u) { - gen_gvec_usra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_ssra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 2: /* VRSHR */ - /* Right shift comes here negative. */ - shift = -shift; - if (u) { - gen_gvec_urshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srshr(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 3: /* VRSRA */ - /* Right shift comes here negative. */ - shift = -shift; - if (u) { - gen_gvec_ursra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } else { - gen_gvec_srsra(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - } - return 0; - - case 4: /* VSRI */ - if (!u) { - return 1; - } - /* Right shift comes here negative. */ - shift = -shift; - gen_gvec_sri(size, rd_ofs, rm_ofs, shift, - vec_size, vec_size); - return 0; - } - if (size == 3) { count = q + 1; } else {