From patchwork Thu May 21 16:39:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foley X-Patchwork-Id: 187052 Delivered-To: patch@linaro.org Received: by 2002:a92:5b0a:0:0:0:0:0 with SMTP id p10csp1727832ilb; Thu, 21 May 2020 10:04:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxMrkzAWpA0d9+6I1OB4t+QUpNXic6b8KKbBn/sM3WpADOMqPWly+LgFH+gADIaIQBZdUs5 X-Received: by 2002:a37:27d7:: with SMTP id n206mr10128739qkn.98.1590080692626; Thu, 21 May 2020 10:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1590080692; cv=none; d=google.com; s=arc-20160816; b=vog/LmWpB+1FbdYdXvDuNqc8h0B6NEr3YInIoKFX7HSCaN/4CaI+iSILMfoeA5MqGv DBjOiOtXSXqnwipNTW8B5IL9dKJ/7W1DlITCPu4HzK1df9IlyEYqaVtb6q/svHOdR/tE ep/2umBuhvfTgzbDTlse0k94Sczcm5UyRLo6X7NtuUklLFQfhYuyGTHDPiFvScD3m1DZ KyPcS8FcsjiTNJzwRMV0wUI7R6WoDXu3UJ7wB7P834nwuRzWzxmlPXNEbIpF+6zPIdkk LhXgU+MOD4OR0i9bJMDHYJSk7NAFbzIGb7mqHBHROSIuAacwqujeTZW+/fokc+uj5ccY ZxiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=EcsY6TGhrUKNyVg3Ugjl3o+5XwjzyMO1Q9LTdSRFfVg=; b=SiJ7pCwp8qc+7BVWegQWwDd1LQ98VEluainK+7k+DnZ4g/JPQA12t0vITLEdYcuS2y JZm2k5pa/t3Z+h9VPrDnK4zMV8oiRDb8aoFnW7LmkVaXT5tJoXU1gk3JawoON6KLapd1 30eHns5uNgfmywzz+oIn0fM58h81dST/yC8YdcdbqI6PRIE0ktsz1KZDJHqk0glkmkpI 4ZbKPoB6nwLwfdSfP1zbYc4qhVBf935kuEtPQbKTYJa0/juPCJuoojS+GVXFQHMEB9CM /R/jsxB5427DigU32p5G/3YV1gUSObpavAks7RLhKgaIoy+cGCaq8M0nnRKfIkSnYAJ2 jxzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W7AF5Djg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k7si3932208qki.266.2020.05.21.10.04.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 May 2020 10:04:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W7AF5Djg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jbocm-0002iH-3d for patch@linaro.org; Thu, 21 May 2020 13:04:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jboIp-0003pS-Jh for qemu-devel@nongnu.org; Thu, 21 May 2020 12:44:15 -0400 Received: from mail-qk1-x742.google.com ([2607:f8b0:4864:20::742]:33288) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jboIo-0006cR-CJ for qemu-devel@nongnu.org; Thu, 21 May 2020 12:44:15 -0400 Received: by mail-qk1-x742.google.com with SMTP id z80so7919470qka.0 for ; Thu, 21 May 2020 09:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EcsY6TGhrUKNyVg3Ugjl3o+5XwjzyMO1Q9LTdSRFfVg=; b=W7AF5Djgi8fFdX2rYkKCq77FDBTeYnp6uw7LfNlHtCyKignaAXSWm5Ap3eo2KUlKea JncBV6e/XRudH8Lnz1R2opmCOrpr5rxhPan0rFZ3BgJjv0FAz2ESDhx1aImSujS95zWo S/mVORkgCdX3tSZoIwNhmLvE1KKJ/fVcl2uQRMXgD3NSDzo3ZL7QeQ5RPrU85ZvruFFL 0qDghS6SNZ+LYCCI/AYHGZ0fI+vdGoJYwfRSQvWoTgMCEasDYS3L8v1uWskQ0GYVO6UJ JT0wv4gePOP19fzB40QZyHQZOPrENwgEploBaJtqYXJGrSxexwD/BVdhFnAe1bDVYqvc XRKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EcsY6TGhrUKNyVg3Ugjl3o+5XwjzyMO1Q9LTdSRFfVg=; b=ubB2tnSwIIE5VCfIVE1Wtw7iCRDBqlMhsTbYgUKP2l/wWQHMipvC++5LiYaZegsRt4 /k46MTFE54Goi37osib7aTnsPxCX86o89711pRi99rKg+FnWzk1WVaQVyHocz28wfgrP ti7vAr0Nf9ZSbIWO0ilMSY9HrOdtB8+pNRI3Ac8ZhrOtzv/gcheEDTo4AxwMuzGaC1DC MqdaTAxL0kwu/VHh7G/6KQGQu77gFBHjg/XwKV/6jE/XqWw3AJ0OzOU/85bgl8Q14UYh 8PpfuBZUGplGEWmcVzaTI8eossi2xnvhaLhekf77QGYF1l8PbuibnGiAjSUixXHp5gOx VfSQ== X-Gm-Message-State: AOAM5326mCzv2BJ21UqkUOa0X1UCFcAeYqeh4DQyfYXQtb+sCB9gYfaz 53w38CTl2Cx5lOwg1hWB1fwzcQvkbomHGA== X-Received: by 2002:a37:b144:: with SMTP id a65mr10559117qkf.462.1590079452888; Thu, 21 May 2020 09:44:12 -0700 (PDT) Received: from Rfoley-MA01.hsd1.ma.comcast.net ([2601:199:4480:60c0:1944:c530:655c:5583]) by smtp.gmail.com with ESMTPSA id x24sm5923829qth.57.2020.05.21.09.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2020 09:44:12 -0700 (PDT) From: Robert Foley To: qemu-devel@nongnu.org Subject: [PATCH v9 43/74] i386/whpx-all: convert to cpu_interrupt_request Date: Thu, 21 May 2020 12:39:40 -0400 Message-Id: <20200521164011.638-44-robert.foley@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200521164011.638-1-robert.foley@linaro.org> References: <20200521164011.638-1-robert.foley@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::742; envelope-from=robert.foley@linaro.org; helo=mail-qk1-x742.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, cota@braap.org, alex.bennee@linaro.org, robert.foley@linaro.org, peter.puhov@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Robert Foley --- target/i386/whpx-all.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index d5beb4a5e2..cb424f04a3 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -752,12 +752,14 @@ static int whpx_handle_portio(CPUState *cpu, static int whpx_handle_halt(CPUState *cpu) { struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr); + uint32_t interrupt_request; int ret = 0; qemu_mutex_lock_iothread(); - if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + interrupt_request = cpu_interrupt_request(cpu); + if (!((interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) && - !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + !(interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index = EXCP_HLT; cpu_halted_set(cpu, true); ret = 1; @@ -775,6 +777,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu = X86_CPU(cpu); int irq; + uint32_t interrupt_request; uint8_t tpr; WHV_X64_PENDING_INTERRUPTION_REGISTER new_int; UINT32 reg_count = 0; @@ -786,17 +789,19 @@ static void whpx_vcpu_pre_run(CPUState *cpu) qemu_mutex_lock_iothread(); + interrupt_request = cpu_interrupt_request(cpu); + /* Inject NMI */ if (!vcpu->interruption_pending && - cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { - if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { + interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { + if (interrupt_request & CPU_INTERRUPT_NMI) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); vcpu->interruptable = false; new_int.InterruptionType = WHvX64PendingNmi; new_int.InterruptionPending = 1; new_int.InterruptionVector = 2; } - if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { + if (interrupt_request & CPU_INTERRUPT_SMI) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); } } @@ -805,12 +810,12 @@ static void whpx_vcpu_pre_run(CPUState *cpu) * Force the VCPU out of its inner loop to process any INIT requests or * commit pending TPR access. */ - if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { - if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && + if (interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { + if ((interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { cpu->exit_request = 1; } - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (interrupt_request & CPU_INTERRUPT_TPR) { cpu->exit_request = 1; } } @@ -819,7 +824,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); - if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + if (interrupt_request & CPU_INTERRUPT_HARD) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); irq = cpu_get_pic_interrupt(env); if (irq >= 0) { @@ -849,7 +854,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) /* Update the state of the interrupt delivery notification */ if (!vcpu->window_registered && - cpu->interrupt_request & CPU_INTERRUPT_HARD) { + cpu_interrupt_request(cpu) & CPU_INTERRUPT_HARD) { reg_values[reg_count].DeliverabilityNotifications.InterruptNotification = 1; vcpu->window_registered = 1; @@ -902,31 +907,33 @@ static void whpx_vcpu_process_async_events(CPUState *cpu) struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu = X86_CPU(cpu); struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu); + uint32_t interrupt_request; - if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && + if ((cpu_interrupt_request(cpu) & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { whpx_cpu_synchronize_state(cpu); do_cpu_init(x86_cpu); vcpu->interruptable = true; } - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_interrupt_request(cpu) & CPU_INTERRUPT_POLL) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); apic_poll_irq(x86_cpu->apic_state); } - if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + interrupt_request = cpu_interrupt_request(cpu); + if (((interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + (interrupt_request & CPU_INTERRUPT_NMI)) { cpu_halted_set(cpu, false); } - if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { + if (interrupt_request & CPU_INTERRUPT_SIPI) { whpx_cpu_synchronize_state(cpu); do_cpu_sipi(x86_cpu); } - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_interrupt_request(cpu) & CPU_INTERRUPT_TPR) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_TPR); whpx_cpu_synchronize_state(cpu); apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, @@ -1413,7 +1420,7 @@ static void whpx_memory_init(void) static void whpx_handle_interrupt(CPUState *cpu, int mask) { - cpu->interrupt_request |= mask; + cpu_interrupt_request_or(cpu, mask); if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu);