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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id z7sm17862531wrt.6.2020.05.31.10.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2020 10:54:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 4/6] exec/cpu-common: Do not restrict CPU to 32-bit memory access maximum Date: Sun, 31 May 2020 19:54:23 +0200 Message-Id: <20200531175425.10329-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200531175425.10329-1-f4bug@amsat.org> References: <20200531175425.10329-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Rikalo , David Hildenbrand , Cornelia Huck , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Beniamino Galvani , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Most CPUs can do 64-bit operations. Update the CPUReadMemoryFunc and CPUWriteMemoryFunc prototypes. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 4 ++-- hw/usb/hcd-musb.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b47e5630e7..5ac766e3b6 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -43,8 +43,8 @@ extern ram_addr_t ram_size; /* memory API */ -typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); -typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); +typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint64_t value); +typedef uint64_t CPUReadMemoryFunc(void *opaque, hwaddr addr); void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); /* This should not be used by devices. */ diff --git a/hw/usb/hcd-musb.c b/hw/usb/hcd-musb.c index c29fbef6fc..4063cbccf8 100644 --- a/hw/usb/hcd-musb.c +++ b/hw/usb/hcd-musb.c @@ -1243,7 +1243,7 @@ static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value) } /* Generic control */ -static uint32_t musb_readb(void *opaque, hwaddr addr) +static uint64_t musb_readb(void *opaque, hwaddr addr) { MUSBState *s = (MUSBState *) opaque; int ep, i; @@ -1305,7 +1305,7 @@ static uint32_t musb_readb(void *opaque, hwaddr addr) }; } -static void musb_writeb(void *opaque, hwaddr addr, uint32_t value) +static void musb_writeb(void *opaque, hwaddr addr, uint64_t value) { MUSBState *s = (MUSBState *) opaque; int ep; @@ -1392,7 +1392,7 @@ static void musb_writeb(void *opaque, hwaddr addr, uint32_t value) }; } -static uint32_t musb_readh(void *opaque, hwaddr addr) +static uint64_t musb_readh(void *opaque, hwaddr addr) { MUSBState *s = (MUSBState *) opaque; int ep, i; @@ -1446,7 +1446,7 @@ static uint32_t musb_readh(void *opaque, hwaddr addr) }; } -static void musb_writeh(void *opaque, hwaddr addr, uint32_t value) +static void musb_writeh(void *opaque, hwaddr addr, uint64_t value) { MUSBState *s = (MUSBState *) opaque; int ep; @@ -1502,7 +1502,7 @@ static void musb_writeh(void *opaque, hwaddr addr, uint32_t value) }; } -static uint32_t musb_readw(void *opaque, hwaddr addr) +static uint64_t musb_readw(void *opaque, hwaddr addr) { MUSBState *s = (MUSBState *) opaque; int ep; @@ -1520,7 +1520,7 @@ static uint32_t musb_readw(void *opaque, hwaddr addr) }; } -static void musb_writew(void *opaque, hwaddr addr, uint32_t value) +static void musb_writew(void *opaque, hwaddr addr, uint64_t value) { MUSBState *s = (MUSBState *) opaque; int ep;