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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , robert.foley@linaro.org, cota@braap.org, "open list:ARM TCG CPUs" , peter.puhov@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is part of a series of changes to remove the implied BQL from the common code of cpu_handle_interrupt and cpu_handle_exception. As part of removing the implied BQL from the common code, we are pushing the BQL holding down into the per-arch implementation functions of do_interrupt and cpu_exec_interrupt. The purpose of this set of changes is to set the groundwork so that an arch could move towards removing the BQL from the cpu_handle_interrupt/exception paths. This approach was suggested by Paolo Bonzini. For reference, here are two key posts in the discussion, explaining the reasoning/benefits of this approach. https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html Signed-off-by: Robert Foley --- target/arm/cpu.c | 13 ++++++++++--- target/arm/helper.c | 17 ++++++++++++++++- 2 files changed, 26 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 401832ea95..b8544f0f0a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -528,12 +528,17 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cs->env_ptr; - uint32_t cur_el = arm_current_el(env); - bool secure = arm_is_secure(env); - uint64_t hcr_el2 = arm_hcr_el2_eff(env); + uint32_t cur_el; + bool secure; + uint64_t hcr_el2; uint32_t target_el; uint32_t excp_idx; + qemu_mutex_lock_iothread(); + cur_el = arm_current_el(env); + secure = arm_is_secure(env); + hcr_el2 = arm_hcr_el2_eff(env); + /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ if (interrupt_request & CPU_INTERRUPT_FIQ) { @@ -568,12 +573,14 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) goto found; } } + qemu_mutex_unlock_iothread(); return false; found: cs->exception_index = excp_idx; env->exception.target_el = target_el; cc->do_interrupt(cs); + qemu_mutex_unlock_iothread(); return true; } diff --git a/target/arm/helper.c b/target/arm/helper.c index c5ea2c25ea..3a22d40598 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9759,7 +9759,13 @@ void arm_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - unsigned int new_el = env->exception.target_el; + unsigned int new_el; + + bool bql = !qemu_mutex_iothread_locked(); + if (bql) { + qemu_mutex_lock_iothread(); + } + new_el = env->exception.target_el; assert(!arm_feature(env, ARM_FEATURE_M)); @@ -9776,6 +9782,9 @@ void arm_cpu_do_interrupt(CPUState *cs) if (arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + if (bql) { + qemu_mutex_unlock_iothread(); + } return; } @@ -9787,6 +9796,9 @@ void arm_cpu_do_interrupt(CPUState *cs) #ifdef CONFIG_TCG if (cs->exception_index == EXCP_SEMIHOST) { handle_semihosting(cs); + if (bql) { + qemu_mutex_unlock_iothread(); + } return; } #endif @@ -9808,6 +9820,9 @@ void arm_cpu_do_interrupt(CPUState *cs) if (!kvm_enabled()) { cpu_interrupt_request_or(cs, CPU_INTERRUPT_EXITTB); } + if (bql) { + qemu_mutex_unlock_iothread(); + } } #endif /* !CONFIG_USER_ONLY */