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[81.40.121.121]) by smtp.gmail.com with ESMTPSA id p14sm18417178wrg.96.2020.08.14.09.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2020 09:39:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/5] hw/timer/avr_timer16: Use the Clock API Date: Fri, 14 Aug 2020 18:39:21 +0200 Message-Id: <20200814163924.11662-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200814163924.11662-1-f4bug@amsat.org> References: <20200814163924.11662-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , Thomas Huth , Joaquin de Andres , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Michael Rolnik , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Expose the 'clkt' clock source. Connect the MCU I/O clock to it. Drop the now unused 'cpu-frequency-hz' static property. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/avr_timer16.h | 3 ++- hw/avr/atmega.c | 3 +-- hw/timer/avr_timer16.c | 12 ++++-------- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/include/hw/timer/avr_timer16.h b/include/hw/timer/avr_timer16.h index 982019d242..fb1ef5d3be 100644 --- a/include/hw/timer/avr_timer16.h +++ b/include/hw/timer/avr_timer16.h @@ -31,6 +31,7 @@ #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/hw.h" +#include "hw/clock.h" enum NextInterrupt { OVERFLOW, @@ -52,6 +53,7 @@ typedef struct AVRTimer16State { MemoryRegion iomem; MemoryRegion imsk_iomem; MemoryRegion ifr_iomem; + Clock *clkin; QEMUTimer *timer; qemu_irq capt_irq; qemu_irq compa_irq; @@ -84,7 +86,6 @@ typedef struct AVRTimer16State { uint8_t ifr; uint8_t id; - uint64_t cpu_freq_hz; uint64_t freq_hz; uint64_t period_ns; uint64_t reset_time_ns; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 9d814de499..f14b558140 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -332,8 +332,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) devname = g_strdup_printf("timer%zu", i); object_initialize_child(OBJECT(dev), devname, &s->timer[i], TYPE_AVR_TIMER16); - object_property_set_uint(OBJECT(&s->timer[i]), "cpu-frequency-hz", - s->xtal_freq_hz, &error_abort); + qdev_connect_clock_in(DEVICE(&s->timer[i]), "clkt", s->ioclk); sbd = SYS_BUS_DEVICE(&s->timer[i]); sysbus_realize(sbd, &error_abort); sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr); diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c index c48555da52..7634fe6587 100644 --- a/hw/timer/avr_timer16.c +++ b/hw/timer/avr_timer16.c @@ -35,6 +35,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "hw/timer/avr_timer16.h" #include "trace.h" @@ -167,7 +168,7 @@ static void avr_timer16_clksrc_update(AVRTimer16State *t16) break; } if (divider) { - t16->freq_hz = t16->cpu_freq_hz / divider; + t16->freq_hz = clock_get_hz(t16->clkin) / divider; t16->period_ns = NANOSECONDS_PER_SECOND / t16->freq_hz; trace_avr_timer16_clksrc_update(t16->freq_hz, t16->period_ns, (uint64_t)(1e6 / t16->freq_hz)); @@ -544,8 +545,6 @@ static const MemoryRegionOps avr_timer16_ifr_ops = { static Property avr_timer16_properties[] = { DEFINE_PROP_UINT8("id", struct AVRTimer16State, id, 0), - DEFINE_PROP_UINT64("cpu-frequency-hz", struct AVRTimer16State, - cpu_freq_hz, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -564,6 +563,8 @@ static void avr_timer16_init(Object *obj) { AVRTimer16State *s = AVR_TIMER16(obj); + s->clkin = qdev_init_clock_in(DEVICE(obj), "clkt", NULL, s); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->capt_irq); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compa_irq); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compb_irq); @@ -587,11 +588,6 @@ static void avr_timer16_realize(DeviceState *dev, Error **errp) { AVRTimer16State *s = AVR_TIMER16(dev); - if (s->cpu_freq_hz == 0) { - error_setg(errp, "AVR timer16: cpu-frequency-hz property must be set"); - return; - } - s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_timer16_interrupt, s); s->enabled = true; }