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[209.51.188.17]) by mx.google.com with ESMTPS id k9si4643026ybf.433.2020.08.21.22.51.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Aug 2020 22:51:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=AZcyokCC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: from localhost ([::1]:44074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k9MRO-0001nk-Vi for patch@linaro.org; Sat, 22 Aug 2020 01:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MR1-0001jW-LJ for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:23 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:23559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MQz-0000DF-En for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598075481; x=1629611481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s+Qui1yOY/DT0/NEtJwMy6JHTS2A8SdJ6rIojxXUwmA=; b=AZcyokCCpiilTAV2BdVyGQ2xaGieuNto19xdDknWHmElxxLbHslLu5nm BRvIuX2YdViyKgtTF/fVGWx260ER4prxC7JEgxIjIFBnHJjQBIBOVZEfC kPORqUn3/MobdH4hohmX7ya+kg+Ql1qBH+UoQGH95N6fiFpic4oXnrsCw DV/PLuv9XTDz88Y8TxIEbKFHWuajqjR13RS/uMs9X4FfGNkUSuyVdVrUW R7CN4tXsvqxlrpJN+LqsfYxtkejl9r3cVfdMNOwk3RZw8oJQ7aVqyLufu xcE59Oi6xwU39UmLjqOTZIKIE+n1Q4v63qh+VbQqUbXpKuxVcmgZ64j4p A==; IronPort-SDR: 2U7UhLOu6S2hS/Gj215hYTrdFY/VIOSbN/SjATPyVBwAcI2OJq8BbmMc2YrfUdWPWtuohFwNFV ow3ogFD0S77PsrywzgcVfMeKPM1tXyLdc9xlHAr2T54dccJrkKm+y0+pvGY3tCJhWILTkDrJqL uK5yDCboNsrlAOE2+gLfxuSwFMMmRJrIMLTntKHtWVvLtsnJ3loACuLHE3DVg+dmK6NMp+3pgf niDG3VTcbyoqqj84aPNDvGRCj2Y2/k+gbqSngfEQfnWGxWKX0AC1qnmow9Q7nkUbnd5hU2F0b9 dWo= X-IronPort-AV: E=Sophos;i="5.76,339,1592841600"; d="scan'208";a="255030529" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:16 +0800 IronPort-SDR: VNipglq2fUV82pVKZL0QSXA1Dv0wXIUYFTg1p9DyO1QGLL9L5tYChBkF3kuTR0AghkCbWlOE2o FstzthWqNkng== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:56 -0700 IronPort-SDR: weEKyVdaZIleEyCJLwMABkCmcTHNAWpBusvqDu9RD1aLrA8oRIgL+iDOsDmewU/8bVuBgaB7BR 2TRNbKcA5vsQ== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Date: Fri, 21 Aug 2020 22:40:43 -0700 Message-Id: <20200822054101.1202175-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:51:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Do not depend on the RVD extension, take input and output via TCGv_i64 instead of fpu regno. Move the function to translate.c so that it can be used in multiple trans_*.inc.c files. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 11 +++++++++++ target/riscv/insn_trans/trans_rvf.c.inc | 16 +--------------- 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.28.0 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0485c0750..1290faddda 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating point values. + * This applies when a 32-bit value is assigned to a 64-bit FP register. + * For consistency and simplicity, we nanbox results even when the RVD + * extension is not present. + */ +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 3bfd8881e7..c7057482e8 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -23,20 +23,6 @@ return false; \ } while (0) -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_fpr(ctx, a->rd); + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); tcg_temp_free(t0); mark_fs_dirty(ctx);